Comparison of DC/DC Converters in DCM for Reducing Low-Frequency Input Current Ripple of Single-Phase Two-Stage Inverters

ABSTRACT

Single-phase two-stage inverters generally use an intermediate capacitor to buffer the power imbalance between DC input and AC output. However, the resultant low-frequency voltage ripple on this intermediate capacitor may produce low frequency ripple at the source side, especially when the front-end dc/dc converter operates in continuous conduction mode (CCM). Some common solutions to reducing this ripple are feed forward control and power decoupling circuits. Alternatively, this paper analyzes a two-stage inverter where the front-end is a dc/dc converter operating in discontinuous conduction mode (DCM). In general dc/dc converters operating in DCM have inherent natural capability to reduce this low-frequency input current ripple, without needing a sophisticated control or complex circuitry as compared with its CCM operation. Analysis with simulation verification is reported to demonstrate such capability.

KEYWORDS

1.      Dc/ac

2.      Low-frequency ripple

3.      Single-phase

4.      Two stage

SOFTWARE: MATLAB/SIMULINK

CIRCUIT DIAGRAM:

Fig. 1. A simplified power-stage diagram of a single-phase two-stage inverter.

EXPECTED SIMULATION RESULTS

          

(a)   CCM operation: _vin = 3:3V

(b) DCM operation: _vin = 0:88V

Fig. 2. DCM boost front-end converter has lower voltage ripple than CCM.

Fig. 3. DCM buck-boost front-end converter does not contain low-frequency

ripple but only high-frequency ripple.

                                                                         

Fig. 4. SEPIC front-end converter operating in DCM+CCM contains negligible

low-frequency ripple but only high-frequency ripple.

Fig. 5. High-gain front-end converter operating in DCM does contains

significant low-frequency ripple.

CONCLUSION

This paper analyzes basic and several higher-order front-end dc/dc converters for single-phase two-stage inverter design. Through inspecting the instantaneous average input current of those converters in discontinuous conduction mode (DCM), it has confirmed that buck-boost converter and buck-boost derived converters such as ZETA are free of low-frequency (mainly double ac line frequency) input current ripple due to the lack of direct connection between input and output during switching actions. For boost converter based converters such as SEPIC and C´ uk converters, their input currents contain lower low-frequency content thanks to the cascaded design. For boost converter based high voltage gain converters, its input current may not necessarily reduce the low-frequency content effectively. It depends on how the high-gain sub circuit is constructed and interacts with the input inductor. Further research is necessary to identify suitable converter topologies which have both smooth input current and low frequency content.

REFERENCES

 [1] K. Fukushima, I. Norigoe, M. Shoyama, T. Ninomiya, Y. Harada, and K. Tsukakoshi, “Input Current-Ripple Consideration for the Pulse-link DC-AC Converter for Fuel Cells by Small Series LC Circuit,” in 2009 Twenty-Fourth Annual IEEE Applied Power Electronics Conference and Exposition, Feb 2009, pp. 447–451.

[2] L. Jianguo, H. Wenbin, Y. Kai, L. Xiaoyu, W. Fuyun, and W. Junji, “Research on input current ripple reduction of two-stage single-phase PV grid inverter,” in 2014 16th European Conference on Power Electronics and Applications, Aug 2014, pp. 1–8.

[3] B. Ge, Y. Liu, H. Abu-Rub, R. S. Balog, F. Z. Peng, S. McConnell, and X. Li, “Current Ripple Damping Control to Minimize Impedance Network for Single-Phase Quasi-Z Source Inverter System,” IEEE Transactions on Industrial Informatics, vol. 12, no. 3, pp. 1043–1054,

June 2016.

[4] Y. Zhou, H. Li, and H. Li, “A Single-Phase PV Quasi-Z-Source Inverter With Reduced Capacitance Using Modified Modulation and Double- Frequency Ripple Suppression Control,” IEEE Transactions on Power Electronics, vol. 31, no. 3, pp. 2166–2173, March 2016.

[5] D. B. W. Abeywardana, B. Hredzak, and V. G. Agelidis, “An Input Current Feedback Method to Mitigate the DC-Side Low-Frequency Ripple Current in a Single-Phase Boost Inverter,” IEEE Transactions on Power Electronics, vol. 31, no. 6, pp. 4594–4603, June 2016.

Improved Particle Swarm Optimization For Photovoltaic System Connected To The Grid With Low Voltage Ride Through Capability

ABSTRACT:

Grid connected photovoltaic (PV) system encounters different types of abnormalities during grid faults; the grid side inverter is subjected to three serious problems which are excessive DC link voltage, high AC currents and loss of grid-voltage synchronization. This high DC link voltage may damage the inverter. Also, the voltage sags will force the PV system to be disconnected from the grid according to grid code. This paper presents a novel control strategy of the two-stage three-phase PV system to improve the Low-Voltage Ride-Through (LVRT) capability according to the grid connection requirement. The non-linear control technique using Improved Particle Swarm Optimization (IPSO) of a PV system connected to the grid through an isolated high frequency DCeDC full bridge converter and a three-phase three level neutral point clamped DC-AC converter (3LNPC2) with output power control under severe faults of grid voltage. The paper, also discusses the transient behavior and the performance limit for LVRT by using a DC-Chopper circuit. The model has been implemented in MATLAB/SIMULINK. The proposed control succeeded to track MPP, achieved LVRT requirements and improving the quality of DC link voltage. The paper show

KEYWORDS:

1.      Particle swarm optimization

2.      Maximum power point tracking

3.      PV system

4.      High frequency isolated converter

5.      Low voltage ride through

6.      Grid

SOFTWARE: MATLAB/SIMULINK

BLOCK DIAGRAM:

Fig. 1. Block diagram of the PV system connected to the grid.

 EXPECTED SIMULATION RESULTS:

Fig. 2. PV module characteristics (a) Current-voltage characteristics (b) power-voltage characteristics.

Fig. 3. Behavior of PV array under normal condition using IPSO.

Fig. 4. DC-link voltage under normal condition using IPSO.

Fig. 5. Behavior of PV array under normal condition using IC.

Fig. 6. DC-link voltage under normal condition using IC.

Fig. 7. Behavior of grid connected inverter system under normal operation.

Fig. 8. The grid voltage fault.

Fig. 9. Behavior of PV array under fault condition.

Fig. 10. DC-link voltage under fault condition.

Fig. 11. Behavior of grid connected inverter system under fault condition.

Fig. 12. Behavior of PV array with LVRT capability.

Fig. 13. DC-link voltage during a grid fault with LVRT capability.

Fig. 14. Behavior of grid connected inverter system with LVRT capability.

CONCLUSION:

Based on the existing grid requirements, this paper discussed the potential of a two-stage three-phase grid-connected PV system operating in grid fault condition. The power control method proposed in this paper is effective when the system is under grid fault operation mode. It can be concluded that the future three-phase grid-connected PV systems are ready to be more active and more “smart” in the regulation of power grid.

Non-linear robust control technique using IPSO control is implemented for MPPT of 100.7 kW PV system connected to the grid. Complete control of both active and reactive powers is implemented using Matlab/Simulink with complete simulation under severe faults of grid voltage. The results show superior behavior of the IPSO; it has a faster dynamic response and better steady-state performance than the traditional algorithm; IC method, thus improving the efficiency of the photovoltaic power generation system. The use of full bridge single phase inverter with a high frequency transformer which combines the advantages of 60 Hz technology and transformer- less inverter technology, achieved MPPT requirements with IPSO. Also, this system overcomes the drawbacks of DC-chopper parameters design.

Two loops of control for the utility-connected 3LNPC2 are implemented which improve the performance of inverter and reduces the harmonics in output voltage. This control, also, increases the power injected to the grid and consequently increases the total efficiency of the system. The results show that the DC chopper circuit is capable of reducing the DC-link voltage below threshold values during the fault and protect it from failure or damage. The IPSO is capable of tracking MPP with LVRT capability included.

An anti-wind up conditioned strategy is used in order to improve the quality on the DC link voltage during and after the grid fault. It succeeds to stop accumulation of the integral part during fault, which helps system to follow up pre-faults values rapidly after clearing the fault. Finally, simulated results have demonstrated the feasibility of the IPSO algorithm and capability of MPPT in grid-connected PV systems with LVRT enhancement.

REFERENCES:

[1] Ramdan B.A. Koad, Ahmed. F. Zobaa, Comparison between the conventional methods and PSO based MPPT algorithm for photovoltaic systems, Int. J. Electr. Electron. Sci. Eng. 8 (2014) 619e624.

[2] Ali Reza Reisi, Mohammad Hassan Moradi, Shahriar Jamas, Classification and comparison of maximum power point tracking techniques for photovoltaic system: a review, Renew. Sustain. Energy Rev. 19 (2013) 433e443.

[3] N.H. Saad, A.A. Sattar, A.M. Mansour, Artificial neural controller for maximum power point tracking of photovoltaic system, in: MEPCON’2006 Conference, II, El-MINIA, Egypt, 2006, pp. 562e567.

[4] Raal Mandour I. Elamvazuthi, Optimization of maximum power point tracking (MPPT) of photovoltaic system using artificial intelligence (AI) algorithms, J. Emerg. Trends Comput. Information Sci. 4 (2013) 662e669.

[5] Saeedeh Ahmadi, Shirzad Abdi, Maximum power point tracking of photovoltaic systems using PSO algorithm under partially shaded conditions, in: The 2nd Cired Regional Conference, Tehran, Iran, 14, 2014, pp. 1e7.

A Modified Three-Phase Four-Wire UPQC Topology With Reduced DC-Link Voltage Rating

ABSTRACT

 The unified power quality conditioner (UPQC) is a custom power device, which mitigates voltage and current-related PQ issues in the power distribution systems. In this paper, a UPQC topology for applications with non-stiff source is proposed. The proposed topology enables UPQC to have a reduced dc-link voltage without compromising its compensation capability. This proposed topology also helps to match the dc-link voltage requirement of the shunt and series active filters of the UPQC. The topology uses a capacitor in series with the interfacing inductor of the shunt active filter, and the system neutral is connected to the negative terminal of the dc-link voltage to avoid the requirement of the fourth leg in the voltage source inverter (VSI) of the shunt active filter. The average switching frequency of the switches in the VSI also reduces, consequently the switching losses in the inverters reduce. Detailed design aspects of the series capacitor and VSI parameters have been discussed in the paper. A simulation study of the proposed topology has been carried out using PSCAD simulator, and the results are presented. Experimental studies are carried out on three-phase UPQC prototype to verify the proposed topology.

KEYWORDS

1.      Average switching frequency

2.      Dc-link voltage

3.      Hybrid topology

4.      Non-stiff source

5.      Unified power quality conditioner (UPQC)

SOFTWARE: MATLAB/SIMULINK

CIRCUIT DIAGRAM:

Fig. 1. Equivalent circuit of proposed VSI topology for UPQC compensated system (modified topology).

EXPECTED SIMULATION RESULTS

   

Fig. 2. Simulation results before compensation (a) load currents (b) terminal voltages.

Fig. 3. Simulation results using conventional topology. (a) DC capacitor voltages (top and bottom). (b) Source currents after compensation. (c) Voltage across the interfacing inductor in phase-a of the shunt active filter. (d) Shunt active filter currents. (e) Terminal voltages with sag, DVR-injected voltages,

and load voltages after compensation.

   

Fig. 4. Simulation results with modified topology. (a) Voltage across series capacitor and load voltage in phase-a. (b) Inverter output voltage in leg-a of shunt active filter. (c) DC and fundamental values of voltage across series capacitor and inverter output voltage.

Fig. 5. Simulation results using modified topology. (a) DC capacitor voltages. (b) Source currents after compensation. (c) Voltage across the interfacing inductor in phase-a of the shunt active filter. (d) Shunt active filter currents. (e) Terminal voltages with sag, DVR injected voltages, and load voltages after compensation.

    

CONCLUSION

A modified UPQC topology for three-phase four-wire system has been proposed in this paper, which has the capability to compensate the load at a lower dc-link voltage under nonstiff source. Design of the filter parameters for the series and shunt active filters is explained in detail. The proposed method is validated through simulation and experimental studies in a three-phase distribution system with neutral-clamped UPQC topology (conventional). The proposed modified topology gives the advantages of both the conventional neutral-clamped topology and the four-leg topology. Detailed comparative studies are made for the conventional and modified topologies. From the study, it is found that the modified topology has less average switching frequency, less THDs in the source currents, and load voltages with reduced dc-link voltage as compared to the conventional UPQC topology.

REFERENCES

[1] M. Bollen, Understanding Power Quality Problems: Voltage Sags and Interruptions. New York: IEEE Press, 1999.

[2] S. V. R. Kumar and S. S. Nagaraju, “Simulation of DSTATCOM and DVR in power systems,” ARPN J. Eng. Appl. Sci., vol. 2, no. 3, pp. 7–13, Jun. 2007.

[3] B. T. Ooi, J. C. Salmon, J. W. Dixon, and A. B. Kulkarni, “A three phase controlled-current PWM converter with leading power factor,” IEEE Trans. Ind. Appl., vol. IA-23, no. 1, pp. 78–84, Jan. 1987.

[4] Y. Ye, M. Kazerani, and V. Quintana, “Modeling, control and implementation of three-phase PWM converters,” IEEE Trans. Power Electron., vol. 18, no. 3, pp. 857–864, May 2003.

[5] R. Gupta, A. Ghosh, and A. Joshi, “Multiband hysteresis modulation and switching characterization for sliding-mode-controlled cascaded multilevel inverter,” IEEE Trans. Ind. Electron., vol. 57, no. 7, pp. 2344–2353, Jul. 2010.

Transformer-less dynamic voltage restorer based on buck-boost converter

ABSTRACT

In this study, a new topology for dynamic voltage restorer (DVR) has been proposed. The topology is inspired by the buck-boost ac/ac converter to produce the required compensation voltage. This topology is able to compensate different voltage disturbances such as sag, swell and flicker without leap of the phase angle. The mass of the proposed topology has been reduced due to lack of injection topology. In addition to, the required compensation energy is directly delivered from the grid through the grid voltage. Therefore, the massive dc-link capacitors are not required to implement. To verify the qualification of the topology, the simulation results by MATLAB/SIMULINK software have been presented. Moreover, an experimental prototype of the case study has been designed and tested.

SOFTWARE: MATLAB/SIMULINK

BLOCK DIAGRAM:

Fig. 1 Proposed topology

EXPECTED SIMULATION RESULTS:

Fig. 2. Simulation results for sag compensation

Fig. 3 Simulation results for swell compensation

Fig. 4. Simulation results

CONCLUSION

In this paper a new topology for DVR using buck-boost ac/ac converter was proposed. This topology contains five bidirectional switches, an inductor and a capacitor. Unlike the conventional topologies, the proposed DVR does not have any injection transformer due to the structural features. Because of direct connection to the grid, the storage elements are not required in the proposed topology. Therefore, this topology has less physical volume, mass and price in comparison with traditional topologies. Any kind of voltage disturbances can be compensated by the proposed topology and the effective operation has been confirmed by simulation and experimental results.

   

REFERENCES

[1]         Hietpas, S.M., Naden, M.: ‘Automatic voltage regulator using an AC voltagevoltage converter’, IEEE Trans. Ind. Appl., 2000, 36, (1), pp. 33–38

[2]         Vilathgamuwa, D.M., Member, S., Perera, A.A.D.R., et al.: ‘Dynamic voltage restorer’, 2003, 18, (3), pp. 928–936

[3]         Wijekoon, H.M., Vilathgamuwa, D.M., Choi, S.S.: ‘Interline dynamic voltage restorer: an economical way to improve interline power quality’, IEE Proc. Gener. Transm. Distrib., 2003, 150, (5), pp. 513–520

[4]         Wang, B., Member, S., Venkataramanan, G., et al.: ‘Operation and control of a dynamic voltage restorer using transformer coupled H-bridge converters’, 2006, 21, (4), pp. 1053–1061

[5]         Babaei, E., Farhadi Kangarlu, M.: ‘Voltage quality improvement by a dynamic voltage restorer based on a direct three-phase converter with fictitious DC link’, IET Gener. Transm. Distrib., 2011, 5, (8), p. 814