Selective Harmonic Mitigation for Cascaded Multilevel Inverters in the Event of Unbalanced Phase Condition

 ABSTRACT

This paper provides the switching angles that mitigate the dominant low-order line-to-line voltage harmonics in a cascaded H-bridge power converter with a single faulty switch. In this paper, first the firing angles for 5-level and 7-level converters are calculated by solving a set of nonlinear equations. Then, in the faulty condition, a set of switching angles for each phase that results in balanced line-to-line voltages is derived. Finally, the provided solutions are used to simulate the faulty operation of a multilevel inverter.

SOFTWARE: MATLAB/SIMULINK

CIRCUIT DIAGRAM

Fig. 1. The seven-level cascaded H-bridge converter.

 EXPECTED SIMULATION RESULTS

Fig. 2. Inverter output voltages in the event of a fault at phase ‘a’. (a) Inverter phase voltages: VaN is the blue waveform (b) Inverter line voltages (c) Inverter load voltages and (d) Harmonic spectrum of the Phase, Line and Load voltages.

CONCLUSION

This paper provided a method to deal with a single fault in a 7-level CHB converter based on SHM method. Using the proposed strategy, the inverter generates balanced line to line voltages in fault condition while the low order harmonics of the load voltages are limited within the acceptable industrial limits (EN 50160 and CIGREWG 36–05). Using the conventional SHM algorithm the maximum achievable line voltage for a seven-level CHB inverter reduces to about 33% in the event of a single fault. While the decrement of output voltage with the proposed fault–tolerant strategy is about 10%. Therefore, the proposed approach improves the maximum achievable fundamental voltage. This strategy can be easily extended and implemented for inverters with more voltage levels.

REFERENCES

[1] Momeni A, Peterman RJ, Beck B, Wu C, Bodapati NB. Effect of Prestressing Wire Indentation Type on the Development Length and Flexural Capacity of Pretensioned Concrete Crossties. ASME. ASME/IEEE Joint Rail Conference, 2015 Joint Rail Conference ():V001T01A026. doi:10.1115/JRC2015-5739.

[2] S. Akhlaghi, N. Zhou, Z. Huang, “Exploring Adaptive Interpolation to Mitigate Non-Linear Impact on Estimating Dynamic States,” IEEE Power Engineering Society General Meeting, Denver, CO, USA, July 2015.

[3] M. Aleenejad, H. Mahmoudi, P. Moamaei and R. Ahmadi, "A New Fault-Tolerant Strategy Based on a Modified Selective Harmonic Technique for Three-Phase Multilevel Converters With a Single Faulty Cell," in IEEE Transactions on Power Electronics, vol. 31, no. 4, pp. 3141-3150, April 2016. doi: 10.1109/TPEL.2015.2444661.

[4] H. Nazaripouya and S. Mehraeen, "Modeling and Nonlinear Optimal Control of Weak/Islanded Grids Using FACTS Device in a Game Theoretic Approach," in IEEE Transactions on Control Systems Technology, vol. 24, no. 1, pp. 158-171, Jan. 2016. doi: 10.1109/TCST.2015.2421434.

[5] V. Dargahi, A. Khoshkbar Sadigh and K. Corzine, "Enhanced double flying capacitor multicell power converter controlled with a new switching pattern," in IET Power Electronics, vol. 8, no. 12, pp. 2386-2395, 12 2015. doi: 10.1049/iet-pel.2014.0738.

New Approach for Harmonic Mitigation in Single Phase Five-Level CHBMI with Fundamental Frequency Switching

ABSTRACT:

The main objective of this paper is to study and analyse the voltage output waveform of a multilevel inverter, to suggest a new approach for harmonic mitigation improving the converter performance. These last type of converters represent a new technology in the field of DC/AC electrical energy conversion, presenting advantages respect to the traditional converters. In fact, the multilevel power converters present a low harmonic content and a high voltage level. The paper considers a five-level single-phase cascaded H-bridge inverter and fundamental frequency modulation techniques. The voltage waveform analysis has allowed to identify a working area of the converter where there are lowest values of the considered harmonic amplitude. The simulated behaviour of the model of the converter, with the logic piloting gate signals, has been obtained  in Matlab-Simulink environment.

KEYWORDS:

1.      Multilevel Power Converter

2.      Soft switching

3.      Phase Shifted Voltage Cancellation

SOFTWARE: MATLAB/SIMULINK

 CIRCUIT DIAGRAM:

Fig. 1. Single-phase five-level CHBMI

 EXPECTED SIMULATION RESULTS:

Fig. 2. Gate signals H-Bridge I with a=~=30°.

Fig. 3. Gate Signals H-Bridge 2 with a=~=30°.

Fig. 4. Voltage trend over time with a=~=30°.

CONCLUSION:

In this paper a fundamental switching modulation strategy for single-phase five-level CHBMI that mitigate low order harmonics is presented. The proposed method, through the control of the a and P parameters, allows the mitigation of third, fifth, seventh, ninth and eleventh harmonics. The values of the control parameters can be obtained without needs to solve a set of nonlinear transcendental equations. However, the fundamental harmonic amplitude can only be varied from 42% to 92% of 2 (Voc*4Yrr.

REFERENCES:

 [I] K. Sivakumar, A. Das, R. Ramchand, C. Patel, and K. Gopakumar, A five-level inverter scheme for a four-pole induction motor drive by feeding the identical voltage-profile windings from both sides, IEEE Trans. Ind. Electron., vol. 57, no. 8,pp. 2776-2784, Aug. 2010.

[2] M. Caruso et a!., Design and experimental characterization of a low-cost, real-time, wireless AC monitoring system based on ATmega 328P-PU microcontroller, 2015 AEIT International Annual Conference (AEIT), Naples, 2015, pp. 1-6. doi: 1O.1109/AEIT.2015.7415267

[3] M. Caruso, R. Miceli, P. Romano, G. Schettino, C. Spataro and F. Viola, A low-cost, real-time monitoring system for PV plants based on ATmega 328P-PU microcontroller, 2015 IEEE International Telecommunications Energy Conference (INTELEC), Osaka, 2015, pp. 1-5. doi: 10.1109/INTLEC2015.7572270

[4] M. Caruso, V. Cecconi, A. O. Di Tommaso, and R. Rocha. A Rotor Flux and Speed Observer for Sensorless Single-Phase Induction Motor Applications. International Journal of Rotating Machinery, vol. 2012, no. 276906, p. 13,2012.

[5] M. Caruso, A O. Di Tommaso, F. Genduso, R. Miceli and G. R. Galluzzo, A DSP-Based Resolver-To-Digital Converter for High-Performance Electrical Drive Applications, in IEEE Transactions on Industrial Electronics, vol. 63, no. 7, pp. 4042- 4051, July 2016.

An Optimized Three Phase Multilevel Inverter Topology with Separate Level and Phase Sequence Generation Part

 ABSTRACT:

 This manuscript presents an optimized, 3-ϕ, multilevel (MLI) inverter topology. The proposed system is derived by cascading the level generation part with the phase sequence generation part. Further, it can be operated at any required level depending upon the configuration of the level generation part. Thus, for higher level operation extra components are required at the level generation part only. Therefore, number of components required for the proposed MLI is lower than the conventional 3-ϕ MLI topologies for higher level operation. Further, the level generation part is shared by the three phases equally. This eliminates the possibility of phase unbalance. The working principle and the operation of the proposed MLI are supported with the simulation and experimental validations. Further, the proposed optimized MLI is also compared with the conventional 3-ϕ MLIs to prove its advantage.

KEYWORDS:

1.      3-ϕ

2.      Multilevel inverter

3.      Common mode voltage

4.      New topology

SOFTWARE: MATLAB/SIMULINK

CIRCUIT DIAGRAM:

Fig. 1. (a) Circuit schematic for the proposed m-level MLI. (b) Configuration of top/bottom BU.

 EXPECTED SIMULATION RESULTS:

Fig 2. Simulation results showing the (a) line to line voltages, (b) Output voltage of top BU, (c) output voltage of bottom BU, (d) phase to neutral voltages and (e) load current waveforms of the proposed 3-ϕ MLI in symmetrical operation.

CONCLUSION:

This paper presents an optimized 3-ϕ MLI configuration with reduced number of component. The prominent features of the proposed MLI are as follows.

1) The proposed MLI configuration is built by cascading LGP and PSGP.

2) For higher level operation only switches required are at the BUs only which resides in the LGP. This reduces the requirement of extra devices compared to conventional topologies.

3) Also, each dc voltage source in the presented MLI topology is equally shared by all the phases. Thus, any chance of inter-phase asymmetry is avoided.

The above mentioned points support that the proposed MLI is an optimized configuration for 3-ϕ operation with reduced number of switches. However, the proposed configuration is operated by using the SVs up-to the red line only. The further work with an improved PWM strategy which takes all the SVs in account, will be presented in the regular paper. This will further increase the number of levels at the output and linearity can be maintained in over-modulation region with improved dc-bus utilization.

REFERENCES:

 [1] J. Rodriguez, J. Lai and F. Z. Peng, "Multilevel inverters: a survey of topologies, controls, and applications," IEEE Trans. Ind. Elect., vol. 49, no. 4, pp. 724-738, Aug. 2002.

[2] K. K. Gupta, A. Ranjan, P. Bhatnagar, L. K. Sahu and S. Jain, "Multilevel Inverter Topologies With Reduced Device Count: A Review," IEEE Trans. Power Elect., vol. 31, no. 1, pp. 135-151, Jan. 2016.

[3] Wu, Bin, and Mehdi Narimani. High-power converters and AC drives. John Wiley & Sons, 2016.

[4] S. S. Fazel, S. Bernet, D. Krug and K. Jalili, "Design and Comparison of 4-kV Neutral-Point-Clamped, Flying-Capacitor, and Series-Connected H-Bridge Multilevel Converters," IEEE Trans. Ind. Appl., vol. 43, no. 4, pp. 1032-1040, July-aug. 2007.

[5] L. Wang, D. Zhang, Y. Wang, B. Wu and H. S. Athab, "Power and Voltage Balance Control of a Novel Three-Phase Solid-State Transformer Using Multilevel Cascaded H-Bridge Inverters for Microgrid Applications," in IEEE Trans. Power Elect., vol. 31, no. 4, pp. 3289-3301, April 2016.

IMPLEMENTATION OF MULTILEVEL DC-LINK INVERTER FOR STANDALONE APPLICATION

ABSTRACT:

In this paper, the details of the implementation of a multilevel dc-link inverter (MLDCLI), suitable for standalone application is presented. The first stage of the MLDCLI is a multilevel dc-link to provide a stepped dc voltage waveform approximating the shape of a rectified sine wave. This rectified sine wave is then inverted after every alternate cycle by a conventional single phase full bridge inverter. MLDCLI requires lesser number of switches thus reducing the number of gate drive circuits and switching complexities as compared to the conventional multilevel inverters (MLI). Hence MLDCLI is chosen for this work. The simulation of nine level cascaded half bridge MLDCLI in closed loop is carried out and results are presented. The hardware implementation of the MLDCLI in square wave staircase operation mode and in-phase level shifted multicarrier sine triangular pulse width modulation mode (IPD-SPWM) is carried out and results are presented. DSP TMS320F28069 is used for the implementation of MLDCLI.

KEYWORDS:

1.      MLI

2.      MLDCLI

3.      Cascaded half bridge MLDCLI

4.      DSP

5.      PI compensator

SOFTWARE: MATLAB/SIMULINK

BLOCK DIAGRAM:

Fig. 1 Generalized block diagram of MLDCLI

 EXPECTED SIMULATION RESULTS:

Fig. 2. Simulation waveforms for closed loop system with kp=19.163 and

ki=22552 (a) Entire waveform (b) Enlarged view

Fig. 3. Harmonic profile of load voltage

Fig. 4. Simulation waveforms for closed loop system

CONCLUSION:

The advantages of a nine level cascaded half bridge MLDCLI is studied, verified by a detailed simulation study and validated experimentally. The substantial reduction in number of components and associated advantages as compared to the conventional MLI makes cascaded half bridge MLDCLI a good choice for high power, medium voltage applications. The closed loop simulation results proved the tracking efficiency of the PI compensator. Square wave and IPDSPWM are the switching schemes selected for the implementation. It is verified from the results of the experimental prototype, that square wave switching scheme requires lower switching frequency and produces lower EMI than IPD-SPWM, but IPD-SPWM scheme has lower voltage THD. The experimental results of a scaled down laboratory prototype of a nine level cascaded half bridge MLDCLI using DSP TMS320F28069 is presented in this paper. The results obtained are in congruence with the theoretical claims and the simulation study.

REFERENCES:

 [1] Samir Kouro, Mariusz Malinowski, K. Gopakumar, Josep Pou, Leopoldo G. Franquelo, Bin Wu, Marcelo A. Pérez, “Recent Advances and Industrial Applications of Multilevel Converters,” IEEE Transactions On Industrial Electronics, vol. 57, no. 8, pp. 2553- 2577, Aug. 2010.

[2] L. G. Franquelo, J. Rodriguez, J. I. Leon, S. Kouro, R. Portillo, and M. A. M. Prats, “The age of multilvel converters arrives,” IEEE Ind.Electron. Mag., vol. 2, no. 2, pp. 28–39, Jun. 2008.

[3] J. Rodriguez, L. G. Franquelo, S. Kouro, J. I. Leon, R. C. Portillo, M. A. M. Prats, and M. A. Perez, “Multilevel converters: An enabling technology for high-power applications,” Proc. IEEE, vol. 97, no. 11, pp. 1786–1817, Nov. 2009.

[4] Gui-Jia Su, “Multilevel DC-Link Inverter”, IEEE Transactions On Industry Applications, vol. 41, no. 3, pp.848 – 854, May/June 2005.

[5] H. Abu-Rub, J. Holtz, J. Rodriguez, and G. Baoming, “Medium voltage multilevel converters—State of the art, challenges, and requirements in industrial applications,” IEEE Trans. Ind. Electron., vol. 57, no. 8, pp. 2581– 2596, Aug. 2010.

A Single-Phase Cascaded Multilevel Inverter Composed of Four-Level Sub-multilevel Cells

 ABSTRACT

This paper presents a novel cascaded multilevel inverter topology. The series connection of proposed basic cells is the main core of this topology. Different methods to determine the values of DC voltage sources in cells are investigated. Advantages and disadvantages of this topology in comparison with classical topologies are discussed. Symmetric and asymmetric structures of this topology are well analyzed through simulations.

KEYWORDS

1.      Cascaded multilevel inverter

2.      Single phase

SOFTWARE: MATLAB/SIMULINK

 GENERAL SCHEMATIC CIRCUIT DIAGRAM:

Fig.. 1. General scheme of proposed cascaded multilevel inverter

EXPECTED SIMULATION RESULTS

Fig. 2. Simulation results of two-cell proposed inverter Symmetric design: (a) va (b) Vaal and iout(c) THD

Asymmetric design: (d) va (e) Vout and iout(f) THD

Fig.3.The blocking voltage of  switches(a) S₁₁ and S₁₂ (b)S₂₁ and  S₂₂  (c)S₃₁ and S₃₂ (d)S₄₁ and S₄₂ (e) S_a (f) S_b  (g) T₁ and T₄ (h)  T₂ and T₃.

 CONCLUSION

In this paper a new structure for multilevel inverters based on series connection of four-level sub-multilevel basic cells is proposed. The H-bridge inverter and additional circuit have been added to the basic form of the proposed inverter in order to generate positive and negative polarities and facilitate the symmetric and asymmetric implementations regarding the values of the dc sources. Different methods are suggested to choose the values of the dc sources and they are appraised by comparison studies with classical cascaded H-bridge inverter. The results of this survey illustrate the fact that the number of switches and the total blocking voltage of the inverter are reduced for the proposed topology compared to the classical ones. Finally, the simulation results on a two-cell inverter with symmetric and asymmetric implementation confirm the proper performance of the proposed topology.

REFERENCES

[I] 1. Franquelo, J. Rodriguez, J. Leon, S. Kouro, R. Portillo, and M. EPrlaectst,ro "nT. hMea ga.g, e of multilevel converters arrives," IEEE Ind. vol. 2, no. 2, pp. 28-39, Jun. 2008.

[2] J. Rodriguez, S. Member, J. Lai, and S. Member, "Multilevel Inverters : A Survey of Topologies , Controls , and Applications," IEEE Trans. Ind. Electron., vol. 49, no. 4, pp. 724-738,2002.

[3] J. Rodriguez, 1. G. Franquelo, S. Kouro, J. I. Leon, R. C. Portillo, M. A. M. Prats, and M. A. Perez, "Multilevel Converters: An Enabling Technology for High-Power Applications," Proc. IEEE, vol. 97, no. II, pp. 1786-1817, Nov. 2009.

[4] J.-S. 1. J.-S. Lai and F. Z. P. F. Z. Peng, "Multilevel converters-a new breed of power converters," lAS '95. Coif. Rec. 1995 IEEE Ind. Appl. Can! Thirtieth lAS Annu. Meet., vol. 3, no. 3, pp. 509-517,1995.

[5] M. Malinowski, K. Gopakumar, J. Rodriguez, and M. A. Perez, E"Ale cStruorvne.,y on Cascaded Multilevel Inverters," IEEE Trans. Ind. vol. 57, no. 7, pp. 2197-2206, Jul. 2010.