ABSTRACT:
Based
on the switched-capacitor (SC) principle, a seven-level inverter is proposed,
which can synthesize seven levels containing a single dc source. Moreover, it
can further generate more levels by a cascaded extension. Meanwhile, the
proposed topology does not require any sensor due to the use of SC technology.
Furthermore, the capacitor voltage is self-balanced without utilizing the
complicated control strategy and additional control circuits. The phase
disposition pulse width modulation (PD-PWM) is adopted to reduce the total
harmonic distortion (THD). The topology can generate the different levels with
a wide range of modulation index. In addition, the topology can also work in
over modulation. Compared with the traditional SC multilevel inverter (MLI),
the absence of H-bridge makes low-voltage stress in proposed topology. The
voltage stress of all switches is not more than the input voltage. Operational
principles, modulation strategy, and voltage stress analysis are discussed.
Simulation and experiment are conducted in low power to verify the feasibility
of the proposed topology.
KEYWORDS:
1. Multilevel inverters
2. Low-voltage
stress
3. Switched-capacitor
4. Voltage self-balancing
SOFTWARE: MATLAB/SIMULINK
Fig.
1. The circuit of the proposed seven-level inverter.
EXPERIMENTAL RESULTS:
Fig.
2. Simulation waveforms of the output voltage and current. (a) Output voltage
and current. (b) THD of the output voltage.
CONCLUSION:
In this paper, the
seven-level inverter is proposed by utilizing the switched capacitor
technology. In addition, the inverter can be used as the basic cell to
construct more output levels through a cascaded configuration. With the PD-PWM
modulation, the capacitor voltage can be self-balanced without any sensor to
detect the voltage. Moreover, the topology can work in different modulation
index and can generate a different number of voltage levels. The working
principle and capacitor parameters are analyzed in detail. In addition, the performances
are compared with the existing topologies to prove the advantages. A low-power
prototype is constructed to prove the feasibility of the proposed topology, and
good performance of steady and transient state is testified.
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