ABSTRACT:
A
seven-level Packed U-Cell inverter is presented in this paper. The converter
uses a single dc source and two floating capacitors, whose voltages are
balanced in open loop, to produce multilevel output voltage. Peak magnitude of
the output phase voltage is equal to the magnitude of dc source. Voltages
across floating capacitors add intermediate voltage-levels by establishing an
asymmetric ratio (with respect to the available dc voltage in the circuit). The
average energy exchange (when the network is in steady state) of the capacitors
with the rest of the inverter-circuit will be zero. This helps the capacitors
to maintain desired voltages and thus create intermediate levels of steady dc voltages.
Performance of the converter is validated in simulation by MATLAB/Simulink and
testing of the converter is done for resistive as well as inductive loads.
Experimental verification of the converter is carried out on a laboratory
prototype and the obtained results match well with the simulation.
KEYWORDS:
1. PUC
converter
2. Natural
balancing
3. Open-loop
control
SOFTWARE: MATLAB/SIMULINK
CONCLUSION:
A seven-level Packed U-Cell converter is
presented. The converter contains only one dc source and two floating capacitors.
Voltages of floating capacitors along with the available dc voltage source
establish a ratio of 3:2:1. Floating capacitors work by the principle of
current-sec balance and therefore have natural balancing capability. Concept of
natural balancing works regardless of the modulation index and load power
factor. Time-domain expressions for the capacitor voltages are derived
considering a specific switching operation of the converter. This helped in
analytically validating the concept of natural balancing. Capacitor requirement
in terms of kJ/MVA is discussed which forms an important aspect of the
converter. Losses and efficiency of the converter are presented in comparison
with few basic topologies including a standard two-level inverter. Performance
of the inverter is validated through extensive simulations in MATLAB/Simulink.
Experimental verification is done by developing a laboratory prototype to
confirm the usefulness of the proposed concept.
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