A Novel Technique for Mitigation of Voltage Sag/Swell by Dynamic Voltage Restorer (DVR)

ABSTRACT

This paper deals with modeling and simulation technique of a Dynamic Voltage Restore (DVR).The DVR is a dynamic solution for protection of critical loads from voltage sags / swells. The DVR restores constant load voltage and voltage wave form by injecting an appropriate voltage. Present novel structure improves power quality by compensating voltage sag and voltage swells. This paper discussed abc to dq0 base new control algorithm to generate the pulse. The proposed control scheme is simple to design and has excellent voltage compensation capabilities. Effectiveness of proposed technique is investigated through computer simulation by using MATLAB/SIMULNK software. The simulation results have shown validation of the control system.

KEYWORDS

         1.        Power Quality

         2.       Voltage sags /swells

         3.      DVR

SOFTWARE: MATLAB/SIMULINK

BLOCK DIAGRAM

                                                  Fig. 1 Basic Principle of DVR

                              Fig. 2 Overall Control circuit of STATCOM based on MATLAB Simulink

SIMULATION RESULTS

                Fig. 3 Supply voltage, injected voltage, load voltage and current for voltage sag effect

Fig. 4 Supply voltage, injected voltage, load voltage and current for voltage swell effect

CONCLUSION

This paper has proposed the modeling and simulation of DVR using simulink in MATLAB. The very simple abc to dqo based control technique used. The steps of developing DVR has been explained in depth. The performance of DVR is studied under voltage sag /swells. The ability of the DVR to compensation of voltage sag/swells has been verified. Simulation result show the DVR mitigates voltage sag /swell very fast and satisfactory in terms of voltage regulation too. The DVR has effectively handled injection of proper voltage component. It can also compensate long duration voltage sag/swell.

REFERENCES

[1]Rakesh Kantaria and S.K.Joshi “A review on power quality problems and solutions” Power electronics National Conference November 2008.

[2]IEEE Std. 1159 – 1995, “Recommended Practice for Monitoring Electric Power Quality.

[3]Yan Li, Chengxiong Mao, Buhan Zhang, Jie Zeng, “Voltage Sag Study for a Practical Industrial Distribution Network”, 2006 International Conference on Power System Technology, pp.1-4, Oct., 2006.

[4]Understanding FACTS: Concepts and Technology of Flexible AC Transmission Systems. Narain G. Hingorani, Laszlo Gyugyi. Wiley IEEE press.

[5] J. G. Nielsen, M. Newman, H. Nielsen,and F. Blaabjerg, “Control and testing of a dynamic voltage restorer (DVR) at medium voltage level,” IEEE Trans.Power Electron., vol. 19, no. 3,p.806,May 2004.

Fault Current Interruption by the Dynamic Voltage Restorer

ABSTRACT

This paper introduces and evaluates an auxiliary control strategy for downstream fault current interruption in a radial distribution line by means of a dynamic voltage restorer (DVR). The proposed controller supplements the voltage-sag compensation control of the DVR. It does not require phase-locked loop and independently controls the magnitude and phase angle of the injected voltage for each phase. Fast least error squares digital filters are used to estimate the magnitude and phase of the measured voltages and effectively reduce the impacts of noise, harmonics, and disturbances on the estimated phasor parameters, and this enables effective fault current interrupting even under arcing fault conditions. The results of the simulation studies performed in the PSCAD/EMTDC software environment indicate that the proposed control scheme: 1) can limit the fault current to less than the nominal load current and restore the point of common coupling voltage within 10 ms; 2) can interrupt the fault current in less than two cycles; 3) limits the dc-link voltage rise and, thus, has no restrictions on the duration of fault current interruption; 4) performs satisfactorily even under arcing fault conditions; and 5) can interrupt the fault current under low dc-link voltage conditions.

KEYWORDS

             1.  Digital filters

      2.  Dynamic Voltage Restorer (DVR),

3.      Fault current interrupting,

4.      Multiloop control.

SCHEMATIC DIAGRAM

                                                           Fig. 1. Schematic diagram of a DVR with a line-side harmonic filter                                           

                                                            Fig. 2. Single-line diagram of the system used for simulation studies.

SIMULATION RESULTS

               Fig. 3. (a) Voltages at Bus₃. (b) Fault currents, during downstream three-phase fault when the DVR is inactive (bypassed).                                       

        Fig. 4. (a) Voltages at Bus₃, (b) Fault currents, during downstream phase –tophase fault when the DVR is inactive (bypassed).

 Fig.5 . (a) Injected voltages. (b) Source voltages. (c) Load voltages. (d) Line currents. (e) DC-link voltage, during the three-phase downstream fault.

Fig. 6. (a) Voltages at Bus₃. (b) Fault currents, during the downstream single phase-to-ground arcing fault when the DVR is inactive (bypassed).

CONCLUSION

This paper introduces an auxiliary control mechanism to enable the DVR to interrupt downstream fault currents in a radial distribution feeder. This control function is an addition to the voltage-sag compensation control of the DVR. The performance of the proposed controller, under different fault scenarios, including arcing fault conditions, is investigated based on time-domain simulation studies in the PSCAD/EMTDC environment. The study results conclude that:

• the proposed multiloop control system provides a desirable transient response and steady-state performance and effectively damps the potential resonant oscillations caused by the DVR LC harmonic filter;

• the proposed control system detects and effectively interrupts the various downstream fault currents within two cycles (of 50 Hz);

• the proposed fault current interruption strategy limits the DVR dc-link voltage rise, caused by active power absorption, to less than 15% and enables the DVR to restore the PCC voltage without interruption; in addition, it interrupts the downstream fault currents even under low dc-link voltage conditions.

• the proposed control system also performs satisfactorily under downstream arcing fault conditions.

REFERENCES

[1] N. G. Hingorani, “Introducing custom power,” IEEE Spectr., vol. 32, no. 6, pp. 41–48, Jun. 1995.

[2] J. G. Nielsen, F. Blaabjerg, and N. Mohan, “Control strategies for dynamic voltage restorer compensating voltage sags with phase jump,” in Proc. IEEE APEC’, 2001, pp. 1267–1273.

[3] G. J. Li, X. P. Zhang, S. S. Choi, T. T. Lie, and Y. Z. Sun, “Control strategy for dynamic voltage restorers to achieve minimum power injection without introducing sudden phase shift,” Inst. Eng. Technol. Gen. Transm. Distrib., vol. 1, no. 5, pp. 847–853, 2007.

[4] S. S. Choi, B. H. Li, and D. M. Vilathgamuwa, “Design and analysis of the inverter-side filter used in the dynamic voltage restorer,” IEEE Trans. Power Del., vol. 17, no. 3, pp. 857–864, Jul. 2002.

[5] B. H. Li, S. S. Choi, and D. M. Vilathgamuwa, “Design considerations on the line-side filter used in the dynamic voltage restorer,” Proc. Inst. Elect. Eng., Gen. Transm. Distrib., vol. 148, no. 1, pp. 1–7, Jan. 2001.

Damping Power System Oscillations Using a Hybrid Series Capacitive Compensation Scheme

Damping Power System Oscillations Using a Hybrid Series Capacitive Compensation Scheme

ABSTRACT:

The recently proposed phase imbalanced series capacitive compensation concept has been shown to be effective in enhancing power system dynamics as it has the potential of damping power swing as well as sub synchronous resonance oscillations. In this paper, the effectiveness of a “hybrid” series capacitive compensation scheme in damping power system oscillations is evaluated. A hybrid scheme is a series capacitive compensation scheme, where two phases are compensated by fixed series capacitor (C) and the third phase is compensated by a TCSC in series with a fixed capacitor (Cc). The effectiveness of the scheme in damping power system oscillations for various network conditions, namely different system faults and tie-line power flows is evaluated using the EMTP-RV time simulation program.

KEYWORDS

1.      FACTS Controllers

2.       phase imbalance

3.       series compensation

4.       thyristor controlled series capacitor

SOFTWARE: MATLAB/SIMULINK

BLOCK DIAGRAM:

Fig. 1. A schematic diagram of the hybrid series compensation scheme.

                                     

Fig. 2. Test benchmark.

EXPECTED SIMULATION RESULTS:

                   

Fig. 3. Generator load angles, measured with respect to generator 1 load angle, during and after clearing a three-phase fault at bus 4 (Load Profile A).

Fig. 4. Generator load angles, measured with respect to generator 1 load angle, during and after clearing a three-phase fault at bus 4 (Load Profile B).

             

Fig. 5. Structure of a dual-channel power oscillations damping controller.

Fig. 6. Generator load angles, measured with respect to generator 1 load angle, during and after clearing a three-phase fault at bus 4 (Load Profile B, dual-channel controller).

Fig. 7. Phase voltages, VX-Y across the hybrid single-phase-TCSC scheme on L1 during and after clearing a three-phase fault at bus 4 (Load Profile B, dual channel supplemental controllers, Pair 2).

CONCLUSION:

The paper presents the application of a new hybrid series capacitive compensation scheme in damping power system oscillations. The effectiveness of the presented scheme in damping these oscillations is demonstrated through several digital computer simulations of case studies on a test

benchmark. The presented hybrid series capacitive compensation scheme is feasible, technically sound, and has an industrial application potential.

REFERENCES:

[1] Narain G. Hingorani and Laszlo Gyugyi, “Understanding FACTS, Concepts and Technology of Flexible AC Transmission Systems,” IEEE Press, 2000.

[2] M. Klein, G.J. Rogers and P. Kundur, “A Fundamental Study of Inter- Area Oscillations in Power Systems,” IEEE Transactions on Power Systems, Vol. 6, No. 3, 1991, pp. 914-921. Fig. 9. Phase voltages, VX-Y across the hybrid single-phase-TCSC scheme on L1 during and after clearing a three-phase fault at bus 4 (Load Profile B, dual channel supplemental controllers, Pair 2).

[3] E.V. Larsen, J.J. Sanchez-Gasca and J.H. Chow, “Concepts for Design of FACTS Controllers to Damp Power Swings,” IEEE Transactions on Power Systems, Vol. 10, No. 2, May 1995, pp. 948-956.

[4] B. Chaudhuri, B. Pal, A. C. Zolotas, I. M. Jaimoukha, and T. C. Green, “Mixed-sensitivity Approach to H Control of Power System Oscillations Employing Multiple FACTS Devices,” IEEE Transactions on Power System, Vol. 18, No. 3, August 2003, pp. 1149–1156.

[5] B. Chaudhuri and B. Pal, “Robust Damping of Multiple Swing Modes Employing Global Stabilizing Signals with a TCSC,” IEEE Transactions on Power System, Vol. 19, No. 1, February 2004, pp. 499–506.

Analysis and Simulation of a D-STATCOM for Voltage Quality Improvement

Analysis and Simulation of a D-STATCOM for Voltage Quality Improvement

ABSTRACT:

Voltage flicker is a major power quality concern for both power companies and customers. This paper discusses the dynamic performance of a (D-STATCOM) with ESS for mitigation of voltage flicker. The (D-STATCOM) is intended to replace the widely used static var compensator (SVC). A Distribution Static Synchronous Compensator (D-STATCOM) is used to regulate voltage on a 25-kV distribution network. The (D-STATCOM) protects the utility transmission or distribution system from voltage sag and /or flicker caused by rapidly varying reactive current demand. The (D-STATCOM) regulates bus voltage by absorbing or generating reactive power. This voltage is provided by a voltage sourced PWM inverter. The simulation is carried out using MATLAB/SIMULINK and the simulation results illustrate the performance of (D-STATCOM) in mitigation of voltage flicker.

KEYWORDS 

1.      Power Quality

2.       Energy Storage System (ESS)

3.       D-STATCOM

4.       Voltage Flicker

5.      Synchronous Reference Frame (SRF)

 SOFTWARE: MATLAB/SIMULINK

BLOCK DIAGRAM:

Fig. 1: D-STATCOM controller with d-q theory.

Fig. 2: Detailed Versus Average Model of D-STATCOM.

EXPECTED SIMULATION RESULTS:

Fig. 3: Output voltage of D-STATCOM.

Fig. 4: Output voltage of voltage source inverter.

Fig. 5: Output P & Q of D-STATCOM.

Fig. 6: Output current of D-STATCOM.

Fig. 7: I_q and I_qref of D-STATCOM.

Fig. 8: P and Q of terminal B₃.

Fig. 9: Terminal voltages B₁ and B₃.

Fig. 10: Changes of DC voltage.

CONCLUSION:

In this paper, D-STATCOM controller is derived by using synchronous reference theory. The model is simulated in MATLAB/SIMULINK platform and D-STATCOM controller’s performance is evaluated using dq theory for voltage flicker mitigation. The controller is proven to be effective for flicker mitigation with improved dynamic response of the system and compensating reactive currents will help the mitigation of voltage flicker.

REFERENCES:

o   Esfandiari, A. and M. Parniani, 2004. “Electric arc furnace power quality improvement using shunt active filter and series inductor,” IEEE Region10 Conference, 4: 105-108.

o   Hingorani, N.G., 1995. “Introducing custom power,” IEEE Spectrum, 1(6): 41-48.

o   Hingorani, N.G. and L. Gyugyi, 2000. “Understanding FACTS: Concepts and Technology of Flexible AC Transmission Systems,” New York: IEEE Press, 135-143.

o   IEEE PES working group FACTS Applications, 1996. IEEE press, (96).

o   Marshall, M.W., 1997. “Using series capacitors to mitigate voltage flicker problems,” 41st Annual Rural Electric Power Conference, pp: B3-1-5