Control of Induction Motor Drive using Space Vector PWM

ABSTRACT

In this paper speed of induction motor is controlled which is fed from three phase bridge inverter. In this paper the speed of an induction motor can be varied by varying input Voltage or frequency or both. Variable voltage and variable frequency for Adjustable Speed Drives (ASD) is invariably obtained from a three-phase Voltage Source Inverter (VSI). Voltage and frequency of inverter can be easily controlled by using PWM techniques, which is a very important aspect in the application of ASDs. A number of PWM techniques are there to obtain variable voltage and variable frequency supply such as PWM, SPWM, SVPWM to name a few, among the various modulation strategies SVPWM is one of the most efficient techniques as it has better performance and output voltage is similar to sinusoidal. In SVPWM the modulation index in linear region will also be high when compared to other.

KEYWORDS

1.      Adjustable Speed Drive (ASD)

2.      Voltage source inverter (VSI)

3.      Sinusoidal PWM (SPWM)

4.      Space Vector PWM (SVPWM)

SOFTWARE: MATLAB/SIMULINK

CIRCUIT DIAGRAM:

 Figure 1. Three-phase voltage source PWM Inverter

EXPECTED SIMULATION RESULTS

Figure 2. Inverter o/p line voltages

Figure 3 Motor Speed and Electromagnetic torque

CONCLUSION

The simulation of “Control of Induction Motor Drive Using Space Vector PWM” is carried out in MATLAB/Simulink. The simulation has been done for open loop as well as closed control. The appropriate output results are obtained. The variation of speed of Induction Motor has been observed by varying the load torque in open loop control and results are noted down in the table. Also observed that for the change in input speed commands the motor speed is settled down to its final value within 0.1sec in closed loop model.

REFERENCES

[1]   Abdelfatah Kolli, Student Member, IEEE, Olivier Béthoux, Member, IEEE, Alexandre De Bernardinis, Member, IEEE, Eric Labouré, and Gérard Coquery “Space-Vector PWM Control Synthesis for an H-Bridge Drive in Electric Vehicles” IEEE TRANSACTIONS ON VEHICULAR TECHNOLOGY, VOL. 62, NO. 6, JULY 2013. pp. 2241-2252.

[2]     Mr. Sandeep N Panchal, Mr. Vishal S Sheth, Mr. Akshay A Pandya “Simulation Analysis of SVPWM Inverter Fed Induction Motor Drives” International Journal of Emerging Trends in Electrical and Electronics (IJETEE) Vol. 2, Issue. 4, April-2013. pp. 18-22 .

[3]        Haoran Shi, Wei Xu, Chenghua Fu and Yao Yang. “Research on Threephase Voltage Type PWM Rectifier System Based on SVPWM Control” Research Journal of Applied Sciences, Engineering and Technology 5(12): 3364-3371, 2013. pp. 3364-3371.

[4]      K. Mounika, B. Kiran Babu, “Sinusoidal and Space Vector Pulse Width Modulation for Inverter” International Journal of Engineering Trends and Technology (IJETT) - Volume4Issue4- April 2013. pp.1012-1017.

[5]         K. Vinoth Kumar, Prawin Angel Michael, Joseph P. John and Dr. S. Suresh Kumar. “Simulation          and Comparison Of Spwm And Svpwm Control For Three Phase Inverter” ARPN Journal of              Engineering and Applied SciencesVOL. 5, NO. 7, JULY 2010. pp. 61-74.

A New Cascaded Switched-Capacitor Multilevel Inverter Based on Improved Series-Parallel Conversion with Less Number of Components

ABSTRACT

 The aim of this study is to present a new structure for switched-capacitor multilevel inverters (SCMLIs) which can generate a great number of voltage levels with optimum number of components for both symmetric and asymmetric value of dc voltage sources. Proposed topology consists of a new switched-capacitor dc/dc converter (SCC) which has boost ability and can charge capacitors as self-balancing by using proposed binary asymmetrical algorithm and series-parallel conversion of power supply. Proposed SCC unit is used in new configuration as a sub-multilevel inverter (SMLI) and then, these proposed SMLIs are cascaded together and create a new cascaded multilevel inverter topology which is able to increase the number of output voltage levels remarkably without using any full H-bridge cell and also can pass the reverse current for inductive loads. In this case, two half bridges modules besides two additional switches are employed in each of SMLI units instead of using a full H-bridge cell which contribute to reduce the number of involved components in the current path, value of blocked voltage, the variety of isolated dc voltage sources and as a result the overall cost by less number of switches in comparison with other presented topologies. The validity of the proposed SCMLI has been carried out by several simulation and experimental results.

KEYWORDS

1.      Cascade sub-multilevel inverter

2.       Series-parallel conversion

3.       Self-charge balancing

4.       Switched-capacitor

SOFTWARE: MATLAB/SIMULINK

CIRCUIT DIAGRAM:

Fig. 1. Proposed 17-level structure

 EXPECTED SIMULATION RESULTS

   

                                                                                      (a)                                                                                                               

 (b)

Fig. 2. Steady states output voltage and current waveforms (a) in simulation Fig. 12. Transient states of output waveforms in simulation (b) in experiment ( 250V/div& 2A/div)

Fig. 3. Transient states of output waveforms in simulation

                   (a)                                                                                                              (b)

Fig. 4. Harmonic orders (a) output voltage (b) output current in simulation

Fig. 5. Observed output voltage waveform at no-load condition

(250V/div)

   

                                                                                                               

                                                                     

    (a)         

(b)

Fig. 6. Capacitors’ voltage ripple waveforms for first case study (a) in simulation (b) in experiment (25 V/dev&50V/div)

     

    

Fig. 7. Blocked voltage waveforms across switches of S₁ (25V/div), S₂ (100V/div), T₁ (50V/div), T₂ and T₃ (100V/div) from left to right in the experiment

 

                                                                                           (a)  

                                                                                                        

                                                                                                (b)

Fig. 8. Output voltage and current waveforms for (a) inductive load in experiment (250 V/div & 2 A/div) (b) sudden step load in simulation

                                                                                                            (a)  

                                                                                   

 

(b)

Fig. 9. Observed capacitors’ current (a) in simulation (b) in experiment (2A/div)

Fig. 10. (a) laboratory prototype (b) Output 49-level voltage and current waveforms in the experiment (250V/div & 2A/div)

Fig. 11. Across voltage waveforms of capacitors in upper and lower stages of SCCs in proposed 49-level inverter (a) v _{C 1} lower stage (5V/div) (b) v _{C 2} lower stage (10V/div) (c) v _{C 1} upper stage(25V/div) (d) v _{C 2} upper stage(50V/div)

CONCLUSION

In this paper, at the first, a new reduced components SCC topology was presented which has boost capability remarkably and also can pass the reverse current for inductive loads through existing power switches. The voltage of all capacitors in this structure is balanced by binary asymmetrical algorithm. Next, a new sub-multilevel structure based on suggested SCC was proposed which can generate all of the voltage levels at the output (even and odd). In this case, the conventional output H-bridge cell used to convert the polarity of SCC units, has been removed, therefore number of required IGBTs and other involved components, are decreased. After that, an optimizing  operation was presented which could obvious the number of required capacitors in each of SCC units that participate in the cascade sub-multilevel inverter (CSMLI) to generate maximum number of output voltage levels with less number of elements. Moreover comprehensive comparisons were given which prove the differences between improved symmetric and asymmetric CSMLIs in contrast to some of recently presented topologies in variety aspects. Finally, to confirm the performance and effectiveness of proposed CSMLI, several simulation and experimental results have been presented.

REFERENCES

[1] J. Chavarria, D. Biel, F. Guinjoan, C. Meza, and J. J. Negroni, “Energy balance control of PV cascaded multilevel grid-connected inverters under level-shifted and phase-shifted PWMs,” IEEE Trans. Ind. Electron. vol. 60, no. 1, pp. 98–111, Jan. 2013.

[2] G. Buticchi, E. Lorenzani, and G. Franceschini, “A five-level single-phase grid-connected converter for renewable distributed systems,” IEEE Trans. Ind. Electron., vol. 60, no. 3, pp. 906–918, Mar. 2013.

[3] J. Rodriguez, L. J.Sheng, and P. Fang Zheng, “Multilevel inverters: A survey of topologies, controls, and applications,” IEEE Trans. Ind Electron., vol. 49, no. 4, pp. 724–738, Aug. 2002.

[4] L. G. Franquelo, J. Rodriguez, J. I. Leon, S. Kouro, R. Portillo, and M. A. M. Prats, “The age of multilevel converters arrives,” IEEE Trans. Industrial Electronic Magazine, vol. 2, no. 2, pp. 28–39, Jun. 2008.

[5] M. M. Renge and H. M. Suryawanshi, “Five-Level Diode Clamped Inverter to Eliminate Common Mode Voltage and Reduce dv/dt in Medium Voltage Rating Induction Motor Drives,” IEEE Trans. Power Electron., vol. 23, no. 4, pp. 1598-1607, Jul. 2008.

Fixed Switching Frequency Sliding Mode Control for Single-Phase Unipolar Inverters

ABSTRACT:

Sliding mode control (SMC) is recognized as robust controller with a high stability in a wide range of operating conditions, although it suffers from chattering problem. In addition, it cannot be directly applied to multi switches power converters. In this paper, a high performance and fixed switching frequency sliding mode controller is proposed for a single-phase unipolar inverter. The chattering problem of SMC is eliminated by smoothing the control law in a narrow boundary layer, and a pulse width modulator produces the fixed frequency switching law for the inverter. The smoothing procedure is based on limitation of pulse width modulator. Although the smoothed control law limits the performance of SMC, regulation and dynamic response of the inverter output voltage are in an acceptable superior range. The performance of the proposed controller is verified by both simulation and experiments on a prototype 6-kVA inverter. The experimental results show that the total harmonic distortion of the output voltage is less than 1.1% and 1.7% at maximum linear and nonlinear load, respectively. Furthermore, the output dynamic performance of the inverter strictly conforms the standard IEC62040-3. Moreover, the measured efficiency of the inverter in the worst condition is better than 95.5%.

KEYWORDS:

1.      Pulse width modulator

2.       Sliding mode control

3.      Unipolar single phase inverter

SOFTWARE: MATLAB/SIMULINK

BLOCK DIAGRAM:

Fig. 1. Proposed controller for single-phase inverters with a resonator in voltage

loop.

 EXPECTED SIMULATION RESULTS:

Fig. 2. Simulation result. a) Output voltage and current at 6-kW linear load. b) Output voltage and current at 6-kVA nonlinear load with CF = 2.75 and PF = +0.7.

Fig. 3. Simulation result: transient response of the output voltage for linear

step load from zero to 100%

.

Fig. 4. Simulation result: transient response of the output voltage for linear

step load from 100% to zero.

Fig. 5. Experimental result: efficiency of inverter versus output power.

CONCLUSION:

In this paper, a fixed frequency SMC was presented for a single-phase inverter. The performance of the proposed controller has been demonstrated by a 6-kVA prototype. Experimental results show that the inverter is categorized in class1 of the IEC64020-3 standard for output dynamic performance. The inverter efficiency was measured up to 95.5% in the worst case.

Since the direct SMC cannot be applied to four switches unipolar inverter and it also suffers from the chattering problem, a PWM is employed to generate a fixed frequency switching law. The PWM modulates the smoothed discontinuous control law which is produced by SMC. To smooth the control law, the limitation of the PWM was considered.

The simulation and experimental results show that the load regulation is about 1% at the steady state as well. But, to obtain better regulation, a resonance compensator was added in the voltage loop. With this compensator, the load regulation was measured which has been below 0.2%.

REFERENCES:

[1] G. Venkataramanan and D.M. Divan, “Discrete time integral sliding mode control for discrete pulse modulated converters,” in Proc. 21st Annu. IEEE Power Electron. Spec. Conf., San Antonio, TX, 1990, pp. 67–73.

[2] J.Y.Hung,W. Gao, and J. C.Hung, “Variable structure control:Asurvey,” IEEE Trans. Ind. Electron., vol. 40, no. 1, pp. 2–22, Feb. 1993.

[3] E. Fossas and A. Ras, “Second order sliding mode control of a buck converter,” in Proc. 41st IEEE Conf. Decision Control, 2002, pp. 346– 347.

[4] C. Rech, H. Pinheiro, H. A. Gr¨undling, H. L. Hey, and J. R. Pinheiro, “A modified discrete control law for UPS applications,” IEEE Trans. Power Electron., vol. 18, no. 5, pp. 1138–1145, Sep. 2003.

[5] K. S. Low, K. L. Zhou, and D.W.Wang, “Digital odd harmonic repetitive control of a single-phase PWM inverter,” in Proc. 30th Annu. Conf. IEEE Ind. Electron. Soc., Busan, Korea, Nov. 2–6, 2004, pp. 6–11.