Evaluation of DVR Capability Enhancement -Zero Active Power Tracking Technique

IEEE, 2016

ABSTRACT:

This paper presents a utilization technique for enhancing the capabilities of dynamic voltage restorers (DVRs). This study aims to enhance the abilities of DVRs to maintain acceptable voltages and last longer during compensation. Both the magnitude and phase displacement angle of the synthesized DVR voltage are precisely adjusted to achieve lower power utilization. The real and reactive powers are calculated in real time in the tracking loop to achieve better conditions. This technique results in less energy being taken out of the DC-link capacitor, resulting in smaller size requirements. The results from both the simulation and experimental tests illustrate that the proposed technique clearly achieved superior performance. The DVR’s active action period was considerably longer, with nearly 5 times the energy left in the DC-link capacitor for further compensation compared to the traditional technique. This technical merit demonstrates that DVRs could cover a wider range of voltage sags; the practicality of this idea for better utilization is better than that of existing installed DVRs.

KEYWORDS:

1.      DVR capability

2.      Energy optimized

3.      Energy source

4.      Series compensator

5.      Voltage stability

SOFTWARE: MATLAB/SIMULINK

BLOCK DIAGRAM:

Fig 1: Single-line diagram of a power system with the DVR connected at PCC.

EXPECTED SIMULATION RESULTS:

Fig.2. D-axis voltages at the system (VSd), DVR (VDVRd), and load (VLd). during in-phase compensation (simulation).

Fig. 3. Q-axis voltages at the system (VSq), DVR (VDVRq), and load (VLq) during in-phase compensation (simulation).

Fig. 4. The overall three-phase voltage signals during in-phase compensation (simulation).

Fig.5 Real power at source (PS), the DVR (PDVR) and load (PL) during in- phase compensation (simulation).

Fig. 6 The DVR DC-side voltage (VDC) during in-phase compensation (simulation).

.Fig. 7. D-axis voltages at the system(VSd), DVR (VDVRd), and load (VLd) during zero-real power tracking compensation (simulation).

Fig. 8.. Q-axis voltages at the system (VSq), DVR (VDVRq), and load (VLq) during zero-real power tracking compensation (simulation).

Fig. 9. The overall three-phase voltage signals during zero-real power tracking compensation (simulation).

Fig. 10. Real power at source (PS), the DVR (PDVR) and load (PL) zero-real power tracking compensation (simulation).

CONCLUSION:

It is clear from both the simulation and experimental results illustrated in this paper that the proposed zero-real power tracking technique applied to DVR-based compensation can result in superior performance compared to the traditional in-phase technique. The experimental test results match those proposed using simulation, although some discrepancies due to the imperfect nature of the test circuit components were seen.

With the traditional in-phase technique, the compensation was performed and depended on the real power injected to the system. Then, more of the energy stored in the DC-link capacitor was utilized quickly, reaching its limitation within a shorter period. The compensation was eventually forced to stop before the entire voltage sag period was finished. When the compensation was conducted using the proposed technique, less energy was used for the converter basic switching process.

The clear advantage in terms of the voltage level at the DC-link capacitor indicates that with the proposed technique, more energy remains in the DVR (67% to 14% in the traditional in-phase technique), which guarantees the correct compensating voltage will be provided for longer periods of compensation. With this technique, none (or less) of the real power will be transferred to the system, which provides more for the DVR to cover a wider range of voltage sags, adding more flexible adaptive control to the solution of sag voltage disturbances.

REFERENCES:

[1]   M. Bollen, Understanding Power Quality Problems, Voltage Sags and Interruptions. New York: IEEE Press, 1999.

[2]   J. Roldán-Pérez, A. García-Cerrada, J. L. Zamora-Macho, P. Roncero-Sánchez, and E. Acha, “Troubleshooting a digital repetitive controller for a versatile dynamic voltage restorer,” Int. J. Elect. Power Energy Syst., vol. 57, pp. 105–115, May 2014.

[3]   P. Kanjiya, B. Singh, A. Chandra, and K. Al-Haddad, “SRF theory revisited to control self-supported dynamic voltage restorer (DVR) for unbalanced and nonlinear loads,” IEEE Trans. Ind. Appl., vol. 49, no. 5, pp. 2330–2340, Sep. 2013.

[4]   S. Naidu, and D. Fernandes, “Dynamic voltage restorer based on a four-leg voltage source converter,” IET Generation, Transmission & Distribution, vol. 3, no. 5, pp. 437–447, May 2009.

[5]   T. Jimichi, H. Fujita, and H. Akagi, “A dynamic voltage restorer equipped with a high-frequency isolated dc-dc converter,” IEEE Trans. Ind. Appl., vol. 47, no. 1, pp. 169–175, Jan. 2011.

Dual-Buck AC–AC Converter with Inverting and Non-Inverting Operations

IEEE Transactions on Power Electronics, 2018

ABSTRACT:

A buck-boost ac-ac converter with inverting and non-inverting operations is proposed. It compensates both the voltage sag and swell when used as a dynamic voltage restorer. Its basic switching cell is a unidirectional buck circuit, owing to which it has no shoot-through concerns. It achieves safe commutation without using RC snubbers or soft commutation strategies. Further, it can be implemented with power MOSFETs without their body diodes conducting, and for current freewheeling external diodes of good reverse recovery features can be used to minimize the reverse recovery issues and relevant loss. The detailed theoretical analysis and experimental results of a 300-W prototype converter are provided.

KEYWORDS:

1.      AC–AC converter

2.      Bipolar voltage gain

3.      Commutation

4.      Dual-buck

5.      DVR

6.      MOSFET

SOFTWARE: MATLAB/SIMULINK

CIRCUIT DIAGRAM:

Fig 1: Proposed buck-boost ac-ac converter

EXPECTED SIMULATION RESULTS:

Fig.2. NIB operation. (a) Input and output voltages and inductor current. (b) Drain-source voltages of switches.

Fig. 3. IBB operation (buck mode). (a) Input and output voltages and inductor current. (b) Drain-source voltages of switches.  

Fig. 4. IBB operation (boost mode). (a) Input and output voltages and inductor current. (b) Drain-source voltages of switches.

Fig.5. INIBB operation (non-inverting buck). (a) Input and output voltages and inductor current. (b) Drain-source voltages of switches.

Fig.6. INIBB operation (inverting buck). (a) Input and output voltages and inductor current. (b) Drain-source voltages of switches.

Fig. 7. INIBB operation (inverting boost). (a) Input and output voltages and inductor current. (b) Drain-source voltages of switches.

Fig. 8. Experimental results with partially inductive load. (a) NIB operation. (b) IBB operation.

Fig. 9. Experimental results with non-linear load in NIB operation.

Fig. 10. Experimental results of the proposed DVR.

CONCLUSION:

In this paper, a novel buck-boost ac-ac converter is proposed. It combined the operations of non-inverting buck and inverting buck-boost converters in one structure. Similar to the buck converter, it has a non-inverting buck operation, and similar to an inverting buck-boost converter, it has an inverting buck-boost operation. In addition, it has an extra operation, in which the output voltage higher or lower than the input voltage that is in-phase or out-of-phase with the input voltage can be obtained. Thus, the proposed converter can compensate both voltage sag and swell when used in a DVR.

The basic unit of the proposed converter is a unidirectional buck circuit, therefore it has no short-circuit and open-circuit problems. It has no commutation problems, and does not require lossy snubbers and/or soft commutation strategies for operation. Further, it can utilize MOSFETs without their body diodes conducting and without reverse recovery issues and relevant losses. A detailed analysis of the proposed converter and DVR has been presented and validated by experimental results.

  

REFERENCES:

[1]   W. E. Brumsickle, R. S. Schneider, G. A. Luckjiff, D. M. Divan, and M. F. McGranaghan, “Dynamic sag correctors: cost-effective industrial power line conditioning,” IEEE Trans. Ind. Appl., vol. 37, no. 1, pp. 212– 217, Jan./Feb. 2001.

[2]   S. Subramanian and M. K. Mishra, “Interphase ac-ac topology for sag supporter,” IEEE Trans. Power Electron., vol. 25, no. 2, pp. 514–518, Feb. 2010.

[3]   IEEE Recommended Practice for Monitoring Electric Power Quality, IEEE Standard 1159-2009 (Revision of IEEE Standard 1159-1995), 2009.

[4]   F. M.-David, S. Bhattacharya and G. Venkataramanan, “A comparative evaluation of series power-flow controllers using dc- and ac-link converters,” IEEE Trans. Power Del., vol. 23, no. 2, pp. 985-996, Apr. 2008.

[5]   D. Francis, and T. Thomas, “Mitigation of voltage sag and swell using dynamic voltage restorer,” 2014 Annual International Conference on Emerging Research Areas: Magnetics, Machines and Drives (AICERA/iCMMD), Kottayam, 2014, pp. 1-6.

Improved Phasor Estimation Method for Dynamic Voltage Restorer Applications

IEEE Transactions on Power Delivery, 2013

ABSTRACT

The dynamic voltage restorer (DVR) is a series compensator for distribution system applications, which protects sensitive loads against voltage sags by fast voltage injection. The DVR must estimate the magnitude and phase of the measured voltages to achieve the desired performance. This paper proposes a phasor parameter estimation algorithm based on a recursive variable and fixed data window Least Error Squares (LES) method for the DVR control system. The proposed algorithm, in addition to decreasing the computational burden, improves the frequency response of the control scheme based on the fixed data window LES method. The DVR control system based on the proposed algorithm provides a better compromise between the estimation speed and accuracy of the voltage and current signals and can be implemented using a simple and low cost processor. The results of the studies indicate that the proposed algorithm is insensitive to noise, harmonics, interharmonics and DC offset unlike the LES method, while both methods estimate the phasor parameters within 5 ms. The performance of the control scheme based on the proposed method is evaluated by multiple case studies in the PSCAD/EMTDC environment and experimentally validated based on a laboratory setup.

KEYWORDS

1.      Dynamic voltage restorer

2.      Phasor estimation

3.      Least Error Squares

4.      Minimum energy

5.      Four-leg inverter

SOFTWARE: MATLAB/SIMULINK

CIRCUIT DIAGRAM:

Fig. 1 Power circuit schematic of the four-wire DVR

EXPECTED SIMULATION RESULTS:

Fig. 2. Sag compensation during SLG fault in the presence of zero sequence component, (a) Grid voltages (V), (b) Estimated grid voltage magnitude of phase A by the improved phasor estimation method, LES, RLS and ADALINE (V), (c) Compensated load voltages (V)

Fig. 3 Sag compensation under nonlinear load conditions, (a) Grid voltages (V), (b) Load currents (A), (c) Compensated load voltages (V)

Fig. 4. Comparison between the improved estimation method, LES, RLS and ADALINE under nonlinear load conditions, (a) Estimated grid voltage magnitude of phase A (V), (b) Estimated grid voltage angle of phase A (rad), (c) Estimated load current angle of phase A (rad)

Fig. 5. Comparison between the improved estimation method, LES, RLS and ADALINE under interharmonics and DC offset conditions, (a) Input signal (p.u.), (b) Estimated magnitude (p.u.), (c) Estimated phase angle (rad)

CONCLUSION

This paper proposes an improved phasor estimation method for DVR control system using a recursive Least Error Squares (LES) method with fixed and variable data window lengths. The proposed algorithm improves the frequency response of the control scheme based on the fixed data window LES in additional to decreasing the computational burden. Thus, it provides a desirable compromise among the speed, accuracy and the amount of computations for the phasor estimation of DVR signals. The experimental and simulation results confirmed that:

1) The estimation time is less than 5 ms and its accuracy increases gradually and it is not sensitive to noise, harmonics, interharmonics and DC offset. Consequently, it is fast and accurate.

2) The proposed algorithm is able to estimate several signal phasors simultaneously in real-time using a low cost processor.

3) The proposed scheme can compensate balanced and unbalanced sag scenarios accurately and within the required time under linear and nonlinear load conditions.

Moreover, during voltage sag compensation, the minimum energy is used and the voltage sags can be compensated without any additional energy storage.

REFERENCES

[1]   P. Fernandez-comesana, F. D. Freijedo, J. Doval-gandoy, O. Lopez, A. G. Yepes, and J. Malvar, ―Mitigation of voltage sags , imbalances and harmonics in sensitive industrial loads by means of a series power line conditioner,‖ Electr. Power Syst. Res., vol. 84, no. 1, pp. 20–30, 2012.

[2]   C. Zhan, V. K. Ramachandaramurthy, A. Arulampalam, C. Fitzer, S. Kromlidis, M. Barnes, and N. Jenkins, ―Dynamic voltage restorer based on voltage-space-vector PWM control,‖ IEEE Trans. Ind. Appl., vol. 37, no. 6, pp. 1855–1863, Nov./Dec. 2001.

[3]   H.-C. So, Y.-S. Lee, and M. H. L. Chow, ―Design of a 1-kVA parallel-type AC voltage sag compensator,‖ IET Power Electron., vol. 5, no. 5, pp. 591– 599, 2012.

[4]   C. Zhan, A. Arulampalam, and N. Jenkins, ―Four-wire dynamic voltage restorer based on a three-dimensional voltage space vector PWM algorithm,‖ IEEE Trans. Power Electron., vol. 18, no. 4, pp. 1093–1102, Jul. 2003.

[5]   P. Roncero-sánchez, E. Acha, J. E. Ortega-calderon, V. Feliu, and A. García-Cerrada, ―A versatile control scheme for a dynamic voltage restorer for power-quality improvement,‖ IEEE Trans. Power Deliv., vol. 24, no. 1, pp. 277–284, Jan. 2009.

Dynamic Voltage Restorer Based on Three-Phase Inverters Cascaded Through an Open-End Winding Transformer

IEEE Transactions on Power Electronics, 2015

ABSTRACT

This paper investigates a dynamic voltage restorer (DVR) composed of two conventional three-phase inverters series cascaded through an open-end winding (OEW) transformer, denominated here DVR-OEW. The DVR-OEW operating with either equal or different dc-link voltages are examined. The proposed topology aims to regulate the voltage at the load side in the case of voltage sags/swells, distortion, or unbalance at the grid voltage. A suitable control strategy is developed, including space-vector analysis, level-shifted PWM (LSPWM) and its equivalent optimized single-carrier PWM (SCPWM), as well as the operating principles and characteristics of the DVR. Comparisons among the DVR-OEW and conventional configurations, including a neutral-point clamped (NPC) converter based DVR, are furnished. The main advantages of the DVROEW compared to the conventional topologies lie on: i) reduced harmonic distortion, ii) reduced converter losses, and iii) reduced voltage rating of the power switches. Simulated and experimental results are presented to validate the theoretical studies.

SOFTWARE: MATLAB/SIMULINK

  

BLOCK DIAGRAM:

Fig. 1 Example of a typical application of DVR in Medium-Voltage (MV) distribution system..

EXPECTED SIMULATION RESULTS:

Fig. 2. System voltages for vca = vcb. (a) Grid voltages (egj). (b) DVR voltages at the secondary side of the injection transformers (vsj ). (c) Load voltages (vlj ). (d) Injected voltage (vp1) for one phase at the primary side of injection transformer.

Fig. 3. Pole voltages in one phase at inverters A (v1a0a) and B (v1b0b), respectively. (a) OEW inverter operates with alternatively leg of converter clamped in every half cycle. (b) OEW inverter operates by clamping inverter A.

CONCLUSION

In this paper a dynamic voltage restorer (DVR) obtained by means of the series connection of two three-phase inverters through an open-end winding transformer was presented. Two equivalent implementations with either level-shifted carrier PWM (LSPWM) or single-carrier PWM (SCPWM) strategy approaches were presented. The main advantages of the proposed topology, compared to conventional configurations with three legs (see Fig. 2(a)), six-leg (see Fig. 2(b)) and NPC (see Fig. 2(c)) lies on: (i) reduced harmonic distortion (operating at the same switching frequency), (ii) reduced converter losses (operating with the same harmonic distortion), (iii) reduced converter losses (with the same switching frequency), see Table III and (iv) reduced voltage rating of the power switches employed in the DVR. The operations with different dc-link voltages have been investigated and it is shown that much lower harmonic distortion can be obtained. The proposed DVR system is suitable for medium voltage application. Simulated and experimental results were also presented.

REFERENCES

[1]         Goharrizi, S. Hosseini, M. Sabahi, and G. Gharehpetian, “Threephase HFL-DVR with independently controlled phases,” Power Electronics, IEEE Transactions on, vol. 27, pp. 1706–1718, April 2012.

[2]         S. Biswas, S. Goswami, and A. Chatterjee, “Optimal distributed generation placement in shunt capacitor compensated distribution systems considering voltage sag and harmonics distortions,” Generation, Transmission Distribution, IET, vol. 8, pp. 783–797, May 2014.

[3]         C. N. M. Ho and H. S. H. Chung, “Implementation and performance evaluation of a fast dynamic control scheme for capacitor-supported interline DVR,” IEEE Trans. Power Electron., vol. 25, pp. 1975 –1988, Aug. 2010.

[4]         J. Rosas-Caro, F. Mancilla-David, J. Ramirez-Arredondo, and A. Bakir, “Two-switch three-phase ac-link dynamic voltage restorer,” Power Electronics, IET, vol. 5, pp. 1754–1763, November 2012.

[5]         S. Subramanian and M. Mishra, “Interphase ac-ac topology for voltage sag supporter,” Power Electronics, IEEE Transactions on, vol. 25, pp. 514 –518, feb. 2010.