A Variable DC Link based Novel Multilevel Inverter Topology for Low Voltage Applications

ABSTRACT:

In this paper; a variable dc link based novel multilevel inverter (MLI) topology is proposed. This proposed topology comprises two variable dc links and a modified H-bridge unit. This new single-phase topology offers advantages such as reduction in count of switches; gate drivers and dc sources while simultaneously improving the power quality. The proposed topology has been analyzed for both symmetric and asymmetric modes of operation. A comparative study of the proposed topology with some recent MLI topologies has been presented. The comparative study indicates that the proposed topology requires less number of dc sources; switches and driver circuits as compared to other topologies. The proposed topology has been simulated for 31- level asymmetric configuration in MATLAB/SIMULINK environment to verify the proper operation of proposed topology. Harmonic analysis was also performed for 31-level inverter which showed significant reduction in the total harmonic distortion (THD) for phase voltage and current waveforms. The proposed topology is suitable for low voltage applications such as standalone photovoltaic (PV) systems and hybrid electric vehicles (HEVs).

KEYWORDS:

1.      Multilevel Inverter

2.      Asymmetric Configuration

3.       Variable DC Link

4.      Reduced Device Count

SOFTWARE: MATLAB/SIMULINK

 CONCLUSION:

In this paper; a novel MLI topology having two variable dc links and a modified H-bridge unit has been proposed for low voltage applications. Generalized form of proposed topology was explained for both symmetric and asymmetric modes of operation from the perspective of quantitative parameters. Through various comparisons made between the proposed asymmetric topology and other reduced device count topologies; it is concluded that the proposed topology requires less number of dc sources; switches and gate drivers as compared with the other presented topologies in literature. However total PIV in proposed topology is found to be slightly higher as compared with the ACHE topology. On the basis of chosen performance indices; proposed topology is found to be more economical as compared to their counterparts. Performance of 31-level proposed asymmetric topology was shown by simulated voltage and current waveforms. Since the switches T5 and T6 in the modified H-bridge have to withstand the total output voltage of MLI; these two switches must be of high voltage rating and hence the proposed topology is best suited for LV applications. The proposed topology also has a distinctive feature of utilizing asymmetric dc sources in a manner to maintain nearly even blocking voltage stress across the switches (TJ to T4) in a modified H-bridge. This feature reduces the number of variety of switches significantly. Harmonic analysis results showed the significant reduction of harmonics in voltage and current waveforms. So there is no need of filter circuit to eliminate harmonics. The proposed topology will be beneficial in LV applications such as standalone PV systems; hybrid electric vehicles (EVs) etc. due to its various benefits. In future; hardware implementation of the proposed topology will be done.

REFERENCES:

[I] L.M. Tolbert; F-Z. Peng and T.G. HabetIer; "Multilevel converters for large electric drives," IEEE Trans. Ind. AppL; vol. 35; no. I; pp. 36-44; Jan.lFeb. 1999.

[2] J. Rodriguez; S. Bernet; B. Wu; J.O. Pontt and S. Kouro,"Multilevel voltage-source-converter topologies for industrial medium-voltage drives," IEEE Trans. Ind. Electron.; vol. 54; no. 6; pp. 2930-2945;Dec. 2007.

[3] J. Rodriguez; J.S. Lai and FL Peng; "Multilevel inverters: A survey of topologies; controls and applications," IEEE Trans. Ind. Electron.; vol. 49; no. 4; pp. 724-738; Aug. 2002.

[4] I. Colak; E. Kabalci and R. Bayindir; "Review of multilevel voltage source inverter topologies and control schemes," Energy Converso Manag.; vol. 52; no. 2; pp. 1114- 1128; 2011.

[5] M. Malinowski; K. Gopakumar; J. Rodriguez and M.A. Perez; "A survey on cascaded multilevel inverters," IEEE Trans. Ind. Electron.; vol. 57; no. 7;p p. 2197-2206; July 20I O. 

A Simplified Space Vector Pulse-Width Modulation Scheme for Three-Phase Cascaded H-bridge Inverters

ABSTRACT:

A simplified space vector pulse-width modulation (SVPWM) for three-phase cascaded H-bridge (CHB) inverters is presented in this paper. Treating each unit as a three-level inverter and adopting serial calculation mode, a CHB inverter is modulated unit by unit using three-level SVPWM. Duty cycles of real sector are obtained by mapping duty cycles of sector 1, in which the calculation of three-level SVPWM is done. The process to implement multilevel SVPWM is simplified to the process to implement three-level SVPWM. By reusing FPGA chip resource which is used for the calculation of three-level SVPWM, the presented SVPWM can be easily adopted to a CHB inverter with different number of units, while the FPGA chip resource utilization is reduced significantly. In addition, the presented SVPWM provides an effective switching frequency higher than the switching frequency of IGBTs. Simulation and experimental results are provided to verify the feasibility of the presented SVPWM.

KEYWORDS:

1.      Three-phase CHB multilevel inverter

2.       Space vector modulation (SVM)

3.      Space vector pulse-width modulation (SVPWM)

4.      Field programmable gate array (FPGA)

 SOFTWARE: MATLAB/SIMULINK

 CONCLUSION:

This paper presents a simplified SVPWM scheme for three-phase CHB inverters. Treating each unit as a three-level inverter and adopting serial calculation mode, a three-phase CHB inverter with n units is modulated unit by unit by using three-level SVPWM instead of using multilevel SVPWM. Then, duty cycles of sector N used to generate gate pulses are obtained by mapping duty cycles of sector 1. Based on principles of the presented SVPWM, the tedious process to implement the conventional multilevel SVPWM is simplified significantly. By reusing FPGA chip resources which are used to do the calculation of three-level SVPWM, the presented SVPWM can be easily adopted to a three-phase CHB inverter with different number of units. Simulation and experimental results are used to validate the presented SVPWM. The presented SVPWM provides a higher effective switching frequency of nfs, while maintains the same dc-link voltage utilization as that of the conventional SVPWM. Compared with the conventional SVPWM, FPGA chip resource utilization of the presented SVPWM is reduced significantly, while the FPGA resource utilization increment of the presented SVPWM is controlled without dramatically increasing.

REFERENCES:

[1] A. Marquez, J. I. Leon, R. Portillo, S. Vazquez, L. G. Franquelo, and S. Kouro, “Adaptive phase-shifted PWM for multilevel cascaded H-bridge converters for balanced or unbalanced operation,” IECON Conf. IEEE Ind. Electron. Society, Yokohama, Japan, Nov. 2015, pp. 5124-5129.

[2] J. Rodriguez, L. G. Franquelo, S. Kouro, J. I. Leon, R. C. Portillo, M. A. M. Prats, and M. A. Perez, “Multilevel Converters: An Enabling Technology for High-Power Applications,” Proc. IEEE, vol. 97, no.11, pp. 1786-1817, Dec. 2009.

[3] H. Abu-Rub, J. Holtz, J. Rodriguez, and G. Baoming, “Medium-Voltage Multilevel Converters—State of the Art, Challenges, and Requirements in Industrial Applications,” IEEE Trans. Ind. Electron., vol. 57, no. 8, pp.2581-2596, Aug. 2010.

[4] C. Lee, B. Wang, S. Chen, S. Chou, J. Huang, P. Cheng, H. Akagi, and P. Barbosa., “Average Power Balancing Control of a STATCOM Based on the Cascaded H-Bridge PWM Converter with Star Configuration,” IEEE Trans. Ind. Appl., vol. 50, no. 6, pp. 3893-3901, Jun. 2014.

[5] S. Essakiappan, H. S. Krishnamoorthy, P. Enjeti, R. S. Balog, and S. Ahmed, “Multilevel Medium-Frequency Link Inverter for Utility Scale Photovoltaic Integration,” IEEE Trans. Power Electron., vol. 30, no.7, pp. 3674-3684, Jul. 2015.

A New Family of Step-up Hybrid Switched-Capacitor Integrated Multilevel InverterTopologies with Dual Input Voltage Sources

ABSTRACT:

In the low voltage based renewable systems like PV and Fuel cell applications, the step-up of the output voltage to drive the loads is essential. For this, the integration of switched-capacitor (SC) units with the dc-ac converters will have the potential advantages like improved efficiency, optimal switching devices, small size of passive elements (L and C) as compared with traditional two-stage conversion system (dc/dc converter and dc/ac converter). This paper focuses on a new family of step-up multilevel inverter topologies with switched capacitor integration with dual input voltage sources. With the flexibility of 2 dc sources and switching capacitor circuits, four different topologies have been suggested in this paper with features of high voltage gain, reduced component count, reduced voltage stress and self-voltage balancing of the capacitor while achieving a higher number of levels. A detailed analysis of proposed multilevel inverters has been analyzed with the symmetrical and asymmetrical mode of operations and the associated gain, the number of levels, and other performance indices are presented. An in-depth study of all the topologies has been accomplished in this paper with several comparative studies in terms of components count, voltage gain and cost. The effectiveness and practicability of the suggested topology with 13 level output voltage has been explained by the experimental results obtained from a scale down prototype.

KEYWORDS:

1.      Hybrid Reduced Switch Bidirectional Cascaded H-Bridge Multilevel Inverter

2.      Pulse Width Modulation (PWM)

3.      Total Harmonics Distortion (THD)

SOFTWARE: MATLAB/SIMULINK

CONCLUSION:

In this paper, a new family of dual input-driven multilevel inverters with the integration of switched-capacitor units for attaining the boost capability as well as multilevel voltage has been discussed. For this, various multilevel inverters have been analyzed with the symmetrical/asymmetrical dc sources as well as different switched capacitor arrangements, and the detailed pros and cons of all configurations are presented. The higher voltage level generation, step-up operation, and lower voltage stress of the switches have been the main features of the proposed topologies. The comparative analysis is provided to highlight the benefits of the proposed topologies over the various multilevel inverters present in the literature. To show the effectiveness of the proposed topologies, a laboratory prototype of PT-I with the symmetrical sources is designed in the laboratory which will produce 13 levels and associated experimental results are provided. Different real-time operating conditions (like a step change in load, power factor, MI, and frequency) have been tested with the proposed topology and the experimental results show good agreement with the simulation results.

REFERENCES:

[1] B. P. Reddy, M. Rao A, M. Sahoo and S. Keerthipati, "A Fault- Tolerant Multilevel Inverter for Improving the Performance of a Pole–Phase Modulated Nine-Phase Induction Motor Drive," IEEE Transactions on Industrial Electronics, vol. 65, no. 2, pp. 1107-1116, Feb. 2018

[2] M. Rawa et al., “Dual input switched-capacitor-based single phase hybrid boost multilevel inverter topology with reduced number of components,” IET Power Electron., vol. 13, no. 4, pp. 881–891, 2020.

[3] P. R. Bana, K. P. Panda, R. T. Naayagi, P. Siano, and G. Panda, “Recently Developed Reduced Switch Multilevel Inverter for Renewable Energy Integration and Drives Application: Topologies, Comprehensive Analysis and Comparative Evaluation,” IEEE Access, vol. 7, pp. 54888–54909, 2019.

[4] J. S. Jagabar and V. Krishnaswamy, “An assessment of recent multilevel inverter topologies with reduced power electronics components for renewable applications,” Renewable and Sustainable Energy Reviews, vol. 82. Elsevier Ltd, pp. 3379– 3399, 01-Feb-2018.

[5] B. P. Reddy and S. Keerthipati, "A Multilevel Inverter Configuration for an Open-End-Winding Pole-Phase-Modulated- Multiphase Induction Motor Drive Using Dual Inverter Principle," IEEE Trans. on Ind. Electron, vol. 65, no. 4, pp. 3035- 3044, April 2018. 

A Multi-Cell 21-Level Hybrid Multilevel Inverter synthesizes a reduced number of components with Voltage Boosting Property

ABSTRACT:

A multi-cell hybrid 21-Level multilevel inverter is proposed in this paper. The proposed topology includes two-unit; an H-bridge is cascaded with a modified K-type unit to generate an output voltage waveform with 21 levels based only on two unequal DC suppliers. The proposed topology's advantage lies in the fine and clear output voltage waveforms with high output efficiency. Meanwhile, the high number of output voltage waveform levels generates a low level of distortion and reduces the level of an electromagnetic interface (EMI). Moreover, it reduces the voltage stress on the switching devices and gives it a long lifetime. Also, the reduction in the number of components has a noticeable role in saving size and cost. Regarding the capacitors charging, the proposed topology presents an online method for charging and balancing the capacitor's voltage without any auxiliary circuits. The proposed topology can upgrade to a high number of output steps through the cascading connection. Undoubtedly this cascading will increase the power level to medium and high levels and reduce the harmonics content to a neglectable rate. The proposed system has been tested through the simulation results, and an experimental prototype based on the controller dSPACE (DS-1103) hardware unit used to support the simulation results.

KEYWORDS:

1.      21-Level Multilevel Inverter (MLI)

2.      Hybridization

3.      Modified K-type inverter

4.      Online charging

5.      Self-balancing

6.      Voltage boosting inverter

7.      Total Harmonic Distortion (THD)

SOFTWARE: MATLAB/SIMULINK

CONCLUSION:

The work in this paper presented a hybrid multilevel inverter that consisted of a series connection between two units (an HB unit with a modified K-Type unit). This combination generates an output voltage waveform with 21 steps. This high number steps in the output voltage help in reducing the level of noises in the output voltage and reduced the stress in the switching devices, which on the one hand generating fine and clear waveforms and on the other hand reduces the harmonic content in the waveforms to a deficient level (satisfying the harmonics standard IEEE519). Economically, the structure of the proposed topology presented an optimal design in terms of reducing the number of switches and DC sources which in turn enhancing the system reliability by reducing the inverter cost. For the capacitors charging process, the paper presents an online method for charging and balancing the capacitor voltages without any auxiliary circuits for that. This helps in the continuous operation of the charging and discharging process for the capacitor without disturbing the process of generating the output voltage. The proposed topology supports the modularity process in order to maximize the range of output power to the medium and high level, and the paper presented two scenarios for the series connection 2HB+K and HB+2K both the cases raise the level of the output power and enhances the system performance to achieve high efficiency. Due to the dependence on multi DC sources, this topology is suitable for renewable energy applications; DC sources are abundant. The hybrid renewable energy sources application will be more appropriate between all the renewable energy applications because the proposed topology-based mainly on two unequal DC suppliers, which will be available easily in the hybrid renewable energy sources.

REFERENCES:

[1] F. Z. Peng, W. Qian, and D. Cao, "Recent advances in multilevel converter/inverter topologies and applications," in The 2010 International Power Electronics Conference-ECCE ASIA-, 2010, pp. 492-501.

[2] J. Rodriguez, J.-S. Lai, and F. Z. Peng, "Multilevel inverters: a survey of topologies, controls, and applications," IEEE Transactions on Industrial Electronics, vol. 49, pp. 724-738, 2002.

[3] L. M. Tolbert and X. Shi, "Multilevel power converters," in Power Electronics Handbook, ed: Elsevier, 2018, pp. 385-416.

[4] K. K. Gupta, A. Ranjan, P. Bhatnagar, L. K. Sahu, and S. Jain, "Multilevel inverter topologies with reduced device count: A review," IEEE transactions on power electronics, vol. 31, pp. 135-151, 2015.

[5] P. Omer, J. Kumar, and B. S. Surjan, "A Review on Reduced Switch Count Multilevel Inverter Topologies," IEEE Access, vol. 8, pp. 22281-22302, 2020.  

A Generalized Multilevel Inverter Topology with Reduction of Total Standing Voltage

ABSTRACT:

  This paper presents a new multilevel inverter topology with reduced active switches and total standing voltage. The proposed topology can generate a high number of voltage levels in the symmetric configuration. This topology intuitively generates positive and negative cycles without an additional H-bridge unit, which considerably reduces the total standing voltage of the inverter. A cascaded structure is developed from the proposed topology to create higher voltage levels. To show the novelty of the proposed topology, a thorough comparison between the available and the proposed topologies in terms of the number of switches, standing voltages, and dc-sources is presented. Furthermore, the power loss analysis is carried out for various load values. The feasibility of the proposed nine-level inverter is verified with simulation and experimental results.

KEYWORDS:

1.      Multilevel inverter

2.       Inverter

3.      Locking voltage

4.      Cascaded structure

5.      Reduced power components

SOFTWARE: MATLAB/SIMULINK

CONCLUSION:

The proposed topology used lower number of power electronics components and reduced dc-sources. Further, the maximum voltage stress on the switch is reduced to 4Vdc for any number of voltage levels in symmetric configuration which is more suitable for medium voltage applications. The simulated and experimental results are presented for various load values. The sudden load changes and modulation index variations are applied to the proposed topology and it corresponding results are given. Further, the power loss and efficiency of propose topology presented for various load power. It is confirming that the proposed topology is more suitable various load changing applications like AC drives, grid connected PV system etc.

REFERENCES:

[1] S. A. Teston, M. Mezaroba, and C. Rech, “Anpc inverter with integrated secondary bidirectional dc port for ess connection,” IEEE Transactions on Industry Applications, vol. 55, no. 6, pp. 7358–7367, 2019.

[2] Jing Huang and K. A. Corzine, “Extended operation of flying capacitor multilevel inverters,” IEEE Transactions on Power Electronics, vol. 21, no. 1, pp. 140–147, 2006.

[3] S. P. Gautam, “Novel h-bridge-based topology of multilevel inverter with reduced number of devices,” IEEE Journal of Emerging and Selected Topics in Power Electronics, vol. 7, no. 4, pp. 2323–2332, 2019.

[4] S. A. A. Ibrahim, A. Palanimuthu, and M. A. J. Sathik, “Symmetric switched diode multilevel inverter structure with minimised switch count,” The Journal of Engineering, vol. 2017, no. 8, pp. 469–478, 2017.

[5] S. S. Lee, M. Sidorov, N. R. N. Idris, and Y. E. Heng, “A symmetrical cascaded compact-module multilevel inverter (ccm-mli) with pulsewidth modulation,” IEEE Transactions on Industrial Electronics, vol. 65, no. 6, pp. 4631–4639, 2018. 

Power Quality Improvement in Solar Fed Cascaded Multilevel Inverter with Output Voltage Regulation Techniques

ABSTRACT:

The presence of harmonics in solar Photo Voltaic (PV) energy conversion system results in deterioration of power quality. To address such issue, this paper aims to investigate the elimination of harmonics in a solar fed cascaded fifteen level inverter with aid of Proportional Integral (PI), Artificial Neural Network (ANN) and Fuzzy Logic (FL) based controllers. Unlike other techniques, the proposed FLC based approach helps in obtaining reduced harmonic distortions that intend to an enhancement in power quality. In addition to the power quality improvement, this paper also proposed to provide output voltage regulation in terms of maintaining voltage and frequency at the inverter output end in compatible with the grid connection requirements. The simulations are performed in the MATLAB / Simulink environment for solar fed cascaded 15 level inverter incorporating PI, ANN and FL based controllers. To exhibit the proposed technique, a 3 kWp photovoltaic plant coupled to multilevel inverter is designed and hardware is demonstrated. All the three techniques are experimentally investigated with the measurement of power quality metrics along with establishing output voltage regulation.

KEYWORDS:

1.      Harmonics

2.      Intelligent control

3.      Multilevel inverter

4.      Photovoltaic's

5.      Power quality

6.      Voltage regulation

SOFTWARE: MATLAB/SIMULINK

CONCLUSION:

The voltage regulation topology along with power quality improvement is considered and implemented both in simulation and experimental setup for a solar fed 15 level inverter. While considering the results, it is found that FLC presents better results for VR while considering the variations at the input solar PV. Despite this, FLC is considered for the nine-level by [23], but the implementation is carried out with the DC power supplies without utilizing the solar panels. All the other methods are implemented for low power and lesser levels of MLI topology. Commercial utilization of MLI by providing the constant output voltage is investigated, and the experimental results prove the effectiveness of the proposed system. The method is applicable for the users require grid interaction along with the power quality improvement.

REFERENCES:

[1] S. Karekezi and T. Ranja, Renewable technologies in Africa. London, U.K.: Zed Books, 1997.

[2] S. Karekezi and W. Kithyoma, ``Renewable energy strategies for rural africa: Is a PV-led renewable energy strategy the right approach for providing modern energy to the rural poor of sub-saharan africa?'' Energy Policy, vol. 30, nos. 11_12, pp. 1071_1086, Sep. 2002.

[3] S. Karekezi andW. Kithyoma, ``Renewable energy in Africa: Prospects and limits in Renewable energy development,'' Workshop Afr. Energy Experts Operationalizing NEPAD Energy Initiative, vol. 1, pp. 1_30, 2-4 Jun. 2003. Jun. 2017. [Online]. Available: https://sustainabledevelopment.un. org/content/documents/nepadkarekezi.pdf

[4] D.-R. Thiam, ``Renewable decentralized in developing countries: Appraisal from microgrids project in senegal,'' Renew. Energy, vol. 35, no. 8, pp. 1615_1623, Aug. 2010.

[5] F. Christoph, World Energy Scenarios: Composing energy futures to 2050. London, U.K.: World Energy Council, 2013. 

Three-Phase Five-Level Grid Synchronized PV Inverter with MPPT for Micro-Grid Application

ABSTRACT:

This paper develops an interesting converter for three phase grid interface for photovoltaic panels. Here a new topology having least number of power semiconductor switches in the five level category is used. The converter consists of three basic sections viz. the photovoltaic source, a two phase inverter and a Scott-T transformer that converts the two-phase inverter output to three phases and connects to the grid. The control system is in the d-q reference frame which provides fast dynamic control response. A maximum power point tracking mechanism (MPPT) is used to generate the direct axis current reference in order to inject the maximum available power into the grid for any insolation. The converter has been designed and developed for 1kW. This is also experimentally validated.

KEYWORDS:

1.      Current referenced control

2.      Maximum Power Point

3.      Sine pulse width modulation

4.      Scott-T Transformer

5.      Isolated Grid Tied Inverter

SOFTWARE: MATLAB/SIMULINK

CONCLUSION:

The paper presents a reduced switched method for generating a five level voltage output from a PV system. The whole converter system consists of three stages, the PV system with MPPT control, the 16 switch two-phase converter and finally isolation stage using Scott-T transformer. The converter pumping the current towards the grid is controlled by taking the PV MPP output current and providing it as Id reference for the inverter. This Id reference current controls the Id value of the inverter current control loop. Two-phase 16 switch inverter topology consist of high frequency and low frequency stages. High frequency stage will have a maximum switching stress voltage of Vdd=2 and similarly low frequency unfolding stage will have a maximum stress voltage of Vdd. The inverter has a self-balanced dc link capacitor pairs without any complex control schemes. Proper simulation analysis for the five level inverter sourced from a PV which in turn fed to grid has done which conforms its application on grid tied applications. Hardware implementation for two-phase level is also made and waveforms were verified comparing with the simulation. Further section of hardware is to be done in future in order to detail verification and making a complete prototype model for analysis.

REFERENCES:

[1] B. Satish Naik , L. Umanand, K. Gopakumar and B. Subba Reddy, ”A New Two-Phase Five-Level Converter for Three-Phase Isolated Grid-Tied Systems With Inherent Capacitor Balancing and Reduced Component Count” IEEE Journal of Emerging and Selected Topics in Power Electronics., VOL. 6, NO. 3,pp 1325-1335 Sep. 2018

[2] Gautam A. Raiker, L. Umanand and B. Subba Reddy, ”Perturb and Observe with Momentum Term applied to Current Referenced Boost Converter for PV Interface” 2018 IEEE International Conference on Power Electronics, Drives and Energy Systems (PEDES)

[3] Gautam A. Raiker , Subba Reddy B., Praveen C. Ramamurthy, L. Umanand, Abines S. G. and Shama G. Vasisht ”Solar PV interface to Grid-Tie Inverter with Current Referenced Boost Converter” 2018 IEEE 13th International Conference on Industrial and Information Systems(ICIIS)

[4] J. Rodrguez, J.-S. Lai, and F. Z. Peng, Multilevel inverters: A survey of topologies, controls, and applications, IEEE Trans. Ind. Electron., vol. 49, no. 4, pp. 724738, Aug. 2002

[5] A. Nabae, I. Takahashi, and H. Akagi, A new neutral-point-clamped PWM inverter, IEEE Trans. Ind. Appl., vol. IA-17, no. 5, pp. 518523, Sep. 1981