ABSTRACT:
Requirement of large number of levels with lower
number of switching devices has made asymmetrical converters more popular than
the symmetrical ones. Asymmetrical cascaded multilevel inverters (ACMLI) can
achieve high efficiency by combining switching devices with different voltage
ratings and technologies. The proposed ACMLI cascades two or more units of
packed U-Cell (PUC) inverters using two or more isolated DC link supplies. In
this paper, one of the PUC unit is controlled using high switching frequency
while the other PUCs are operated in a step mode at low switching frequencies,
thus operating them in a variable frequency control mode. The cascading of two
7-level PUC inverters with DC link voltage ratios of 1:7 can produce an output
voltage with 49 (7x7) levels. The multi-level output voltage waveform is nearly
sinusoidal with very low THD content, and the low switching frequency operation
leads to lower power dissipation and greater system efficiency. However, each
PUC module requires two dc voltage sources. To address this concern, in this
manuscript, each PUC module consists of one dc voltage source and one dc bus
capacitor. With the cascaded PUC topology and proposed control algorithm, load
current and dc bus capacitor voltage control is achieved simultaneously. The
proposed converter and its control technique lead to the breaking of the design
trade-off rule between switching frequency (efficiency) and filter size. This
is very useful in various applications such as Uninterruptible Power Supplies (UPS),
and grid-tie inverters. The converter and its control technique are simulated
using MATLAB/Simulink software and simulation results for both open loop and
closed loop are discussed. Hardware results are obtained by developing a 1-KW
experimental prototype. Simulation and experimental results confirm the
usefulness and effectiveness of the proposed topology and its control
technique.
KEYWORDS:
1. Asymmetric cascaded
multilevel inverters
2. Total Harmonic Distortion
3. Variable frequency
control
4. Packed U-Cell inverters
5. Low switching frequency
SOFTWARE: MATLAB/SIMULINK
CONCLUSION:
This paper presented a cascaded Packed
U-Cell inverter with forty-nine output voltage levels offering a reduced switch
count solution. Only two auxiliary capacitors along with two isolated dc
voltage sources are used to achieve forty-nine levels in the output voltage
waveform. Between the two cascaded PUCs, one cell operates at high switching
frequency (2 kHz) and other unit is operating at seven time the fundamental
frequency (350 Hz). DC link voltage ratio of the two PUCs is kept at 1:7 to
achieve the maximum forty-nine level output voltage. Detailed explanation of
level formation and individual PUC output voltages are also discussed.
Presented control algorithm achieves dc bus capacitor voltage and load current
control simultaneously. Simulation results are discussed in detail for both
open loop and closed loop performances. Accurate and robust control of dc bus
capacitor control is achieved during load current variation as shown in
transient response of the system. Experimental results validate voltage levels
formation in individual PUC module and formation of resultant 49 – levels in
output voltages. THD spectrum of load voltage and load current are also
presented (in both simulation and experimental results), which verify the
superior THD performance.
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