Control Scheme to Improve DPFC Performance during Series Converter Failures

ABSTRACT

The Distributed Power Flow Controller (DPFC) is a new device within the FACTS family. It is emerged from the UPFC and has relatively low cost and a high reliability. The DPFC consists of two types of converters that are in shunt and series connected to grids. The common dc link between the shunt and the series converters is eliminated. The active power exchange between the shunt and series converters that is through the common dc link in the UPFC, is now though the transmission line at the 3rd harmonic frequency. The redundancy of the series converters provides the high reliability of the system. In this paper, the DPFC behavior during the failure of a single series converter unit is considered. A control scheme to improve the DPFC performance during the failure is proposed. The principle of the control is based on the facts that, the failure of single series converter will lead to unsymmetrical current at the fundamental frequency. By controlling the negative and zero sequence current to zero, the failure of the series converter is compensated. In this paper, the principle of the DPFC are firstly introduced, and followed by the behavior of the DPFC during the failure of a single series converter. The design of the control scheme and corresponding simulation are presented.

KEYWORDS

1.      Power Flow Control

2.      Flexible AC Transmission System

3.      Current Control

4.      symmetrical component

5.      Voltage Source Converter

6.      Transmission

7.      Distributed Power Flow Controller

8.      Unified Power Flow Controller.

SOFTWARE: MATLAB/SIMULINK

BLOCK DIAGRAM

 SIMULATION RESULTS

CONCLUSION

This paper analyzed the DPFC performance during a failure of a single series converter unit. Series converters are protected by crowbar diodes to prevent over-voltage at the secondary side of the single-turn transformer. Therefore the failed series converter unit appears short-circuit to the transmission line and the voltage injection is unbalanced between phases. Because of this unbalance, the power network becomes asymmetric thereby resulting unsymmetrical current at the fundamental frequency. Also, the 3rd harmonic current that used to be zero sequence contains positive and negative components thereby leaking to rest of networks. A supplementary control scheme is proposed to add at the DPFC central control to improve the DPFC performance during series converter failure. Its principle is to monitor the zero and negative sequence components of the line current and control them to be zero. The control scheme has been simulated in Matlab, and it proved that the asymmetric caused by the failure can be totally compensated.

REFERENCES

[1] Z. Yuan, S. W. H. de Haan, and B. Ferreira, “A new facts component: Distributed power flow controller (dpfc),” in Power Electronics and Applications, 2007 European Conference on, 2007, pp. 1–4.

[2] L. Gyugyi, “Unified power-flow control concept for flexible ac transmission systems,” Generation, Transmission and Distribution [see also IEE Proceedings-Generation, Transmission and Distribution], IEE Proceedings C, vol. 139, no. 4, pp. 323–331, 1992.

[3] D. Divan and H. Johal, “Distributed facts - a new concept for realizing grid power flow control,” in Power Electronics Specialists Conference, 2005. PESC ’05. IEEE 36th, 2005, pp.8 14.

[4] M. Milosevic, G. Andersson, and S. Grabic, “Decoupling current control and maximum power point control in small power network with photovoltaic source,” in Power Systems Conference and Exposition, 2006. PSCE ’06. 2006 IEEE PES, 2006, pp. 1005–1011.

[5] J. Salaet, S. Alepuz, A. Gilabert, and J. Bordonau, “Comparison between two methods of dq transformation for single phase converters control. application to a 3-level boost rectifier,” in Power Electronics Specialists Conference, 2004. PESC 04. 2004 IEEE 35th Annual, vol. 1, 2004, pp. 214–220 Vol.1.

Simulation of MRAS-based Speed Sensorless Estimation of Induction Motor Drives using MATLAB/SIMULINK

ABSTRACT

Model Reference Adaptive System (MRAS) based techniques are one of the best methods to estimate the rotor speed due to its performance and straightforward stability approach. These techniques use two different models (the reference model and the adjustable model) which have made the speed estimation a reliable scheme especially when the motor parameters are poorly known or having large variations. The scheme uses the error vector from the comparison of both models as the feedback for speed estimation. Depending on the type of tuning signal driving the adaptation mechanism, there could be a number of schemes available such as rotor flux based MRAS, back e.m.f based MRAS, reactive power based MRAS and artificial neural network based MRAS. All these schemes have their own trends and tradeoffs. In this paper, the performance of the rotor flux based MRAS (RF-MRAS) and back e.m.f based MRAS (BEMF-MRAS) for estimating the rotor speed was studied. Both schemes use the stator equation and rotor equation as the reference model and the adjustable model respectively. The output error from both models is tuned using a PI controller yielding the estimated rotor speed. The dynamic response of the RF-MRAS and BEMF-MRAS sensorless speed estimation is examined in order to evaluate the performance of each scheme.

KEYWORDS

         1.      BEMF-MRAS

         2.      MRAS

         3.      Parameter Variations

         4.      RFMRAS

         5.      Sensorless Speed

         6.      Tracking Capability.

SOFTWARE: MATLAB/SIMULINK

BLOCK DIAGRAM

Fig. 1. Basic configuration of MRAS-based speed sensorless estimation

scheme.

Fig. 2. Block diagram of RF-MRAS scheme

Fig. 3. Block diagram of BEMF-MRAS scheme.

   SIMULATION RESULTS

Fig. 4. RF-MRAS estimator's tracking performance at reference speed (a) 100rad/s, (b) 70rad/s and (c) 50rad/s (d) 30rad/s.

Fig. 5. Effect of incorrect setting of RS values to the RF-MRAS estimator's speed response. (a) Rs (b) Rsnew = 1.1 Rs (C) Rsnew = 1.5 Rs (d) Rsnew = 2 RS.

Fig. 6. BEMF-MRAS estimator's tracking performance at reference speed (a) 100rad/s, (b) 70rad/s and (c) 50rad/s (d) 30rad/s.

Fig. 7. Effect of incorrect setting of Rs values to the BEMF-MRAS estimator's speed response. (a) Rs (b) Rs,ew = 1.1 Rs (c) Rs,ew = 1.5 Rs (d) Rs,ew = 2 Rs.

CONCLUSION

Performance of RF-MRAS and BEMF-MRAS estimators based on the tracking capability and parameter sensitivity was presented. The result shows that the BEMFMRAS estimator is more superior to the RF-MRAS estimator at that particular defined range of reference speeds. This is prior to the elimination of pure integrators used in the RF-MRAS scheme. However, the BEMF-MRAS estimator is more difficult to design due to the non-linear effect of the adaptation gain constants. Therefore, as a whole, considering all the key criteria of comparison, it can be concluded that the BEMF-MRAS scheme embrace the requirement as a versatile estimator. It demonstrate good tracking capability and superb in insensitivity to parameter variations.

REFERENCES

[1] M. Ta-Cao, Y. Hori and T. Uchida, "MRAS-based speed sensorless control for induction motor drives using instantaneous reactive power", IEEE-IES Conference Record, pp. 1717-1422. 2001.

[2] S. Tamai, H. Sugimoto, M. Yano, "Speed-sensorless vector control of induction motor with model reference adaptive system", Conf. Record of the 1985 IEEE-IAS Annual Meeting, pp. 613-620, 1985.

[3] C. Shauder, "Adaptive speed identification for vector control of induction motor without rotational transducers", IEEE Trans. Ind. Application, Vol. 28, No. 5, pp. 1054-1061, Sept./Oct. 1992.

[4] Y.P. Landau, "Adaptive Control: The model reference approach", Marcel Dekker, New York, 1979.

[5] M.N. Marwali, A. Kehyani, "A comparative study of rotor flux based MRAS and back e.m.f based MRAS speed estimators for speed sensorless vector control of induction machine", IEEE-IAS Annual Meeting, New Orleans, Louisiana, pp. 160- 166, 1997.

Harmonic Mitigation using Fuzzy Logic Controller based Shunt Active Power Filter

ABSTRACT

Power quality problem is t he most sensitive problem in the power system. The objective of the project is to reduce one of the power quality issue called “harmonics” using compensation technique. Shunt Active Power Filter (SAPF) is used to eliminate harmonic current and also it compensates reactive power. In this project, both PI controller and Fuzzy Logic Controller based three-phase shunt active filter is employed for a three-phase four wire systems. The advantage of fuzzy control is that it provides linguistic values such as low, medium, high that are useful in case where the probability of the event to occur is needed. It does not require an accurate mathematical model of the system. A MATLAB/SIMULINK has been used to perform the simulation. Simulink model is developed for three phase four wire system under balanced source condition and three phase four wire system for unbalanced source condition. The performance of both balanced source and unbalanced source is done using Fuzzy Logic Controller and PI controller and their Simulink results is compared. Simulation results obtained shows that the performance of fuzzy controller is found to be better than PI controller.

KEYWORDS

       1.      Logic Control

       2.      Instantaneous p-q theory

       3.      Shunt Active Power Filter.

SOFTWARE: MATLAB/SIMULINK

BLOCK DIAGRAM

 Fig 1: Block diagram of proposed system

 Fig 2: Structure of three phase four wire APF

SIMULATION RESULTS

 Fig 3: Simulation Waveform using pq with PI                 

 Fig 4: Simulation Waveform using pq with FLC          

 

 Fig 5: Harmonic Spectrum of Is using PI for balanced source

 Fig 6: Harmonic Spectrum of Is using FLC for balanced source

 Fig 7: Harmonic Spectrum of Is using PI for unbalanced source     

                 

                                                 Fig. 8 Harmonic Spectrum of Is using FLC for unbalanced source                                                                

CONCLUSION

The comparative analysis of a three phase four wire system using SAPF for reducingTHD of source current is done.The analysis uses the control of compensating current using PI controller and FLC is done for both balanced and unbalanced source condition. The harmonic spectrum shows the THD of both balanced and unbalanced source condition using PI and FLC. It is found that the harmonic reduction using FLC is found to produce better result than PI controller.

 REFERENCES

[1] Akagi. H. 2005. Active Harmonic Filters. Proceedings of the IEEE, Vol.93, 2128-2141.

[2] Hirofumi Akagi, Yoshihira Kanazawa and Akira Nabae. (1984), “Instantaneous Reactive Power Compensators Comprising Switching Devices without Energy Storage Components”, IEEE Transactions on Industrial Electronics, Vol. 20, pp-625-630.

[3] Fang Zheng Peng and Akagi.H, (1990), “A New Approach to harmonic Compensation in Power Systems –Acombined System of Shunt Passive and Series Active Filters”, IEEE Transactions on Industrial Applications, Vol. 26, pp-6-11.

[4] Karuppanan P and Kamala kanta Mahapatra (2011), “PI with Fuzzy Logic Controller based Active Power Line Condtioners” Asian Power Electronics, Vol. 5, pp-464-468.

[5] Kirawanich P and O,Connell R.M. (2004), “Fuzzy Logic Control of an Active Power Line Condioner”, (2004), IEEE Transactions on Power Electronics, Vol. 19, pp-1574-1585.

Implementation of Z-Source Based Dynamic Voltage Restorer for the Mitigation of Voltage Sag /Swell

 ABSTRACT

Modern industrial equipments are more sensitive to power quality problems such as voltage sag, voltage swells, interruption, harmonic, flickers and impulse transient. Failures due to such disturbances create high impact on production cost. So nowadays high quality power is became basic needs of highly automated industries This paper deals with modeling and simulation technique of a Dynamic Voltage Restore (DVR).The DVR is a dynamic solution for protection of critical loads from voltage sags/swells. The DVR restores constant load voltage and voltage wave form by injecting an appropriate voltage. Present novel structure improves power quality by compensating voltage sag and voltage swells. This control scheme provides superior performance compared to conventional control methods because it directly measurers the rms voltage at the load point without involving any transformation process. A new topology based on Z-source inverter is presented in order to enhance the voltage restoration property of dynamic voltage restorer. Z-source inverter would ensure a constant DC voltage across the DC-link during the process of voltage compensation. The modeling of Z-source based dynamic voltage restorer is carried out component wise and their performances are analyzed using MATLAB software.

KEYWORDS

      1.      Point Of Common Coupling (PCC)

      2.      Dynamic Voltage Restorer (DVR)

      3.      Active Power Filter (APF)

SOFTWARE: MATLAB/SIMULINK

BLOCK DIAGRAM

 Fig.1. Schematic diagram of DVR.

Fig.2. Proposed Z source inverter topology.

SIMULATION RESULTS

 Fig.3. Simulation waveform of DVR based system when sag occurred. 

 Fig.4. Simulation waveform of DVR based system when swell occurred.

 Fig.5. Simulation waveform of DVR based system when sag/swell occurred.

Fig.6. Simulation waveform of DVR based system when connected to Z-source inverter.

CONCLUSION

Simulation of Z-source DVR for Power Quality Improvement is one of the techniques to improve the power quality by using Z-source DVR. This project has presented a discrete PWM control scheme for Dynamic Voltage Restorer to improve the system response and injection capability for the mitigation of voltage sag/swell. As opposed to fundamental frequency switching schemes already available in the MATLAB/SIMULINK, this PWM control scheme requires only rms value of the voltage.

REFERENCES

[1] M.H.J Bollen „Understanding Power Quality Problems : Voltage sag and Interruptions” New York IEEE Press ,1999.

[2] J.C. smith J.Lamoree ,P.Vinett,T.Duffy M.Klein “The impact of voltage sag Industrial plant load” International Conference Power quality end use application and perspective pp171-178.

[3] Akagi H,”New trends in active filters for power conditioning” IEEE Transaction Ind.Application,vol 32 pp 1312-1322 Nov/Dec 1996.

[4] Ghosh A and Ledwich G (2002) “Power quality Enhancement using Custom Power Devices”.Kluwr Academics publishers, United States.

[5] O. Anaya-Lara, E. Acha, “Modeling and Analysis of Custom Power Systems by PSCAD/EMTDC,” IEEE Trans., Power Delivery, PWDR vol-17 (1), pp. 266-272, 2002.

A Novel Technique for Mitigation of Voltage Sag/Swell by Dynamic Voltage Restorer (DVR)

ABSTRACT

This paper deals with modeling and simulation technique of a Dynamic Voltage Restore (DVR).The DVR is a dynamic solution for protection of critical loads from voltage sags / swells. The DVR restores constant load voltage and voltage wave form by injecting an appropriate voltage. Present novel structure improves power quality by compensating voltage sag and voltage swells. This paper discussed abc to dq0 base new control algorithm to generate the pulse. The proposed control scheme is simple to design and has excellent voltage compensation capabilities. Effectiveness of proposed technique is investigated through computer simulation by using MATLAB/SIMULNK software. The simulation results have shown validation of the control system.

KEYWORDS

         1.        Power Quality

         2.       Voltage sags /swells

         3.      DVR

SOFTWARE: MATLAB/SIMULINK

BLOCK DIAGRAM

                                                  Fig. 1 Basic Principle of DVR

                              Fig. 2 Overall Control circuit of STATCOM based on MATLAB Simulink

SIMULATION RESULTS

                Fig. 3 Supply voltage, injected voltage, load voltage and current for voltage sag effect

Fig. 4 Supply voltage, injected voltage, load voltage and current for voltage swell effect

CONCLUSION

This paper has proposed the modeling and simulation of DVR using simulink in MATLAB. The very simple abc to dqo based control technique used. The steps of developing DVR has been explained in depth. The performance of DVR is studied under voltage sag /swells. The ability of the DVR to compensation of voltage sag/swells has been verified. Simulation result show the DVR mitigates voltage sag /swell very fast and satisfactory in terms of voltage regulation too. The DVR has effectively handled injection of proper voltage component. It can also compensate long duration voltage sag/swell.

REFERENCES

[1]Rakesh Kantaria and S.K.Joshi “A review on power quality problems and solutions” Power electronics National Conference November 2008.

[2]IEEE Std. 1159 – 1995, “Recommended Practice for Monitoring Electric Power Quality.

[3]Yan Li, Chengxiong Mao, Buhan Zhang, Jie Zeng, “Voltage Sag Study for a Practical Industrial Distribution Network”, 2006 International Conference on Power System Technology, pp.1-4, Oct., 2006.

[4]Understanding FACTS: Concepts and Technology of Flexible AC Transmission Systems. Narain G. Hingorani, Laszlo Gyugyi. Wiley IEEE press.

[5] J. G. Nielsen, M. Newman, H. Nielsen,and F. Blaabjerg, “Control and testing of a dynamic voltage restorer (DVR) at medium voltage level,” IEEE Trans.Power Electron., vol. 19, no. 3,p.806,May 2004.

Fault Current Interruption by the Dynamic Voltage Restorer

ABSTRACT

This paper introduces and evaluates an auxiliary control strategy for downstream fault current interruption in a radial distribution line by means of a dynamic voltage restorer (DVR). The proposed controller supplements the voltage-sag compensation control of the DVR. It does not require phase-locked loop and independently controls the magnitude and phase angle of the injected voltage for each phase. Fast least error squares digital filters are used to estimate the magnitude and phase of the measured voltages and effectively reduce the impacts of noise, harmonics, and disturbances on the estimated phasor parameters, and this enables effective fault current interrupting even under arcing fault conditions. The results of the simulation studies performed in the PSCAD/EMTDC software environment indicate that the proposed control scheme: 1) can limit the fault current to less than the nominal load current and restore the point of common coupling voltage within 10 ms; 2) can interrupt the fault current in less than two cycles; 3) limits the dc-link voltage rise and, thus, has no restrictions on the duration of fault current interruption; 4) performs satisfactorily even under arcing fault conditions; and 5) can interrupt the fault current under low dc-link voltage conditions.

KEYWORDS

             1.  Digital filters

      2.  Dynamic Voltage Restorer (DVR),

3.      Fault current interrupting,

4.      Multiloop control.

SCHEMATIC DIAGRAM

                                                           Fig. 1. Schematic diagram of a DVR with a line-side harmonic filter                                           

                                                            Fig. 2. Single-line diagram of the system used for simulation studies.

SIMULATION RESULTS

               Fig. 3. (a) Voltages at Bus₃. (b) Fault currents, during downstream three-phase fault when the DVR is inactive (bypassed).                                       

        Fig. 4. (a) Voltages at Bus₃, (b) Fault currents, during downstream phase –tophase fault when the DVR is inactive (bypassed).

 Fig.5 . (a) Injected voltages. (b) Source voltages. (c) Load voltages. (d) Line currents. (e) DC-link voltage, during the three-phase downstream fault.

Fig. 6. (a) Voltages at Bus₃. (b) Fault currents, during the downstream single phase-to-ground arcing fault when the DVR is inactive (bypassed).

CONCLUSION

This paper introduces an auxiliary control mechanism to enable the DVR to interrupt downstream fault currents in a radial distribution feeder. This control function is an addition to the voltage-sag compensation control of the DVR. The performance of the proposed controller, under different fault scenarios, including arcing fault conditions, is investigated based on time-domain simulation studies in the PSCAD/EMTDC environment. The study results conclude that:

• the proposed multiloop control system provides a desirable transient response and steady-state performance and effectively damps the potential resonant oscillations caused by the DVR LC harmonic filter;

• the proposed control system detects and effectively interrupts the various downstream fault currents within two cycles (of 50 Hz);

• the proposed fault current interruption strategy limits the DVR dc-link voltage rise, caused by active power absorption, to less than 15% and enables the DVR to restore the PCC voltage without interruption; in addition, it interrupts the downstream fault currents even under low dc-link voltage conditions.

• the proposed control system also performs satisfactorily under downstream arcing fault conditions.

REFERENCES

[1] N. G. Hingorani, “Introducing custom power,” IEEE Spectr., vol. 32, no. 6, pp. 41–48, Jun. 1995.

[2] J. G. Nielsen, F. Blaabjerg, and N. Mohan, “Control strategies for dynamic voltage restorer compensating voltage sags with phase jump,” in Proc. IEEE APEC’, 2001, pp. 1267–1273.

[3] G. J. Li, X. P. Zhang, S. S. Choi, T. T. Lie, and Y. Z. Sun, “Control strategy for dynamic voltage restorers to achieve minimum power injection without introducing sudden phase shift,” Inst. Eng. Technol. Gen. Transm. Distrib., vol. 1, no. 5, pp. 847–853, 2007.

[4] S. S. Choi, B. H. Li, and D. M. Vilathgamuwa, “Design and analysis of the inverter-side filter used in the dynamic voltage restorer,” IEEE Trans. Power Del., vol. 17, no. 3, pp. 857–864, Jul. 2002.

[5] B. H. Li, S. S. Choi, and D. M. Vilathgamuwa, “Design considerations on the line-side filter used in the dynamic voltage restorer,” Proc. Inst. Elect. Eng., Gen. Transm. Distrib., vol. 148, no. 1, pp. 1–7, Jan. 2001.