Improved Phasor Estimation Method for Dynamic Voltage Restorer Applications

IEEE Transactions on Power Delivery, 2013

ABSTRACT

The dynamic voltage restorer (DVR) is a series compensator for distribution system applications, which protects sensitive loads against voltage sags by fast voltage injection. The DVR must estimate the magnitude and phase of the measured voltages to achieve the desired performance. This paper proposes a phasor parameter estimation algorithm based on a recursive variable and fixed data window Least Error Squares (LES) method for the DVR control system. The proposed algorithm, in addition to decreasing the computational burden, improves the frequency response of the control scheme based on the fixed data window LES method. The DVR control system based on the proposed algorithm provides a better compromise between the estimation speed and accuracy of the voltage and current signals and can be implemented using a simple and low cost processor. The results of the studies indicate that the proposed algorithm is insensitive to noise, harmonics, interharmonics and DC offset unlike the LES method, while both methods estimate the phasor parameters within 5 ms. The performance of the control scheme based on the proposed method is evaluated by multiple case studies in the PSCAD/EMTDC environment and experimentally validated based on a laboratory setup.

KEYWORDS

1.      Dynamic voltage restorer

2.      Phasor estimation

3.      Least Error Squares

4.      Minimum energy

5.      Four-leg inverter

SOFTWARE: MATLAB/SIMULINK

CIRCUIT DIAGRAM:

Fig. 1 Power circuit schematic of the four-wire DVR

EXPECTED SIMULATION RESULTS:

Fig. 2. Sag compensation during SLG fault in the presence of zero sequence component, (a) Grid voltages (V), (b) Estimated grid voltage magnitude of phase A by the improved phasor estimation method, LES, RLS and ADALINE (V), (c) Compensated load voltages (V)

Fig. 3 Sag compensation under nonlinear load conditions, (a) Grid voltages (V), (b) Load currents (A), (c) Compensated load voltages (V)

Fig. 4. Comparison between the improved estimation method, LES, RLS and ADALINE under nonlinear load conditions, (a) Estimated grid voltage magnitude of phase A (V), (b) Estimated grid voltage angle of phase A (rad), (c) Estimated load current angle of phase A (rad)

Fig. 5. Comparison between the improved estimation method, LES, RLS and ADALINE under interharmonics and DC offset conditions, (a) Input signal (p.u.), (b) Estimated magnitude (p.u.), (c) Estimated phase angle (rad)

CONCLUSION

This paper proposes an improved phasor estimation method for DVR control system using a recursive Least Error Squares (LES) method with fixed and variable data window lengths. The proposed algorithm improves the frequency response of the control scheme based on the fixed data window LES in additional to decreasing the computational burden. Thus, it provides a desirable compromise among the speed, accuracy and the amount of computations for the phasor estimation of DVR signals. The experimental and simulation results confirmed that:

1) The estimation time is less than 5 ms and its accuracy increases gradually and it is not sensitive to noise, harmonics, interharmonics and DC offset. Consequently, it is fast and accurate.

2) The proposed algorithm is able to estimate several signal phasors simultaneously in real-time using a low cost processor.

3) The proposed scheme can compensate balanced and unbalanced sag scenarios accurately and within the required time under linear and nonlinear load conditions.

Moreover, during voltage sag compensation, the minimum energy is used and the voltage sags can be compensated without any additional energy storage.

REFERENCES

[1]   P. Fernandez-comesana, F. D. Freijedo, J. Doval-gandoy, O. Lopez, A. G. Yepes, and J. Malvar, ―Mitigation of voltage sags , imbalances and harmonics in sensitive industrial loads by means of a series power line conditioner,‖ Electr. Power Syst. Res., vol. 84, no. 1, pp. 20–30, 2012.

[2]   C. Zhan, V. K. Ramachandaramurthy, A. Arulampalam, C. Fitzer, S. Kromlidis, M. Barnes, and N. Jenkins, ―Dynamic voltage restorer based on voltage-space-vector PWM control,‖ IEEE Trans. Ind. Appl., vol. 37, no. 6, pp. 1855–1863, Nov./Dec. 2001.

[3]   H.-C. So, Y.-S. Lee, and M. H. L. Chow, ―Design of a 1-kVA parallel-type AC voltage sag compensator,‖ IET Power Electron., vol. 5, no. 5, pp. 591– 599, 2012.

[4]   C. Zhan, A. Arulampalam, and N. Jenkins, ―Four-wire dynamic voltage restorer based on a three-dimensional voltage space vector PWM algorithm,‖ IEEE Trans. Power Electron., vol. 18, no. 4, pp. 1093–1102, Jul. 2003.

[5]   P. Roncero-sánchez, E. Acha, J. E. Ortega-calderon, V. Feliu, and A. García-Cerrada, ―A versatile control scheme for a dynamic voltage restorer for power-quality improvement,‖ IEEE Trans. Power Deliv., vol. 24, no. 1, pp. 277–284, Jan. 2009.

Dynamic Voltage Restorer Based on Three-Phase Inverters Cascaded Through an Open-End Winding Transformer

IEEE Transactions on Power Electronics, 2015

ABSTRACT

This paper investigates a dynamic voltage restorer (DVR) composed of two conventional three-phase inverters series cascaded through an open-end winding (OEW) transformer, denominated here DVR-OEW. The DVR-OEW operating with either equal or different dc-link voltages are examined. The proposed topology aims to regulate the voltage at the load side in the case of voltage sags/swells, distortion, or unbalance at the grid voltage. A suitable control strategy is developed, including space-vector analysis, level-shifted PWM (LSPWM) and its equivalent optimized single-carrier PWM (SCPWM), as well as the operating principles and characteristics of the DVR. Comparisons among the DVR-OEW and conventional configurations, including a neutral-point clamped (NPC) converter based DVR, are furnished. The main advantages of the DVROEW compared to the conventional topologies lie on: i) reduced harmonic distortion, ii) reduced converter losses, and iii) reduced voltage rating of the power switches. Simulated and experimental results are presented to validate the theoretical studies.

SOFTWARE: MATLAB/SIMULINK

  

BLOCK DIAGRAM:

Fig. 1 Example of a typical application of DVR in Medium-Voltage (MV) distribution system..

EXPECTED SIMULATION RESULTS:

Fig. 2. System voltages for vca = vcb. (a) Grid voltages (egj). (b) DVR voltages at the secondary side of the injection transformers (vsj ). (c) Load voltages (vlj ). (d) Injected voltage (vp1) for one phase at the primary side of injection transformer.

Fig. 3. Pole voltages in one phase at inverters A (v1a0a) and B (v1b0b), respectively. (a) OEW inverter operates with alternatively leg of converter clamped in every half cycle. (b) OEW inverter operates by clamping inverter A.

CONCLUSION

In this paper a dynamic voltage restorer (DVR) obtained by means of the series connection of two three-phase inverters through an open-end winding transformer was presented. Two equivalent implementations with either level-shifted carrier PWM (LSPWM) or single-carrier PWM (SCPWM) strategy approaches were presented. The main advantages of the proposed topology, compared to conventional configurations with three legs (see Fig. 2(a)), six-leg (see Fig. 2(b)) and NPC (see Fig. 2(c)) lies on: (i) reduced harmonic distortion (operating at the same switching frequency), (ii) reduced converter losses (operating with the same harmonic distortion), (iii) reduced converter losses (with the same switching frequency), see Table III and (iv) reduced voltage rating of the power switches employed in the DVR. The operations with different dc-link voltages have been investigated and it is shown that much lower harmonic distortion can be obtained. The proposed DVR system is suitable for medium voltage application. Simulated and experimental results were also presented.

REFERENCES

[1]         Goharrizi, S. Hosseini, M. Sabahi, and G. Gharehpetian, “Threephase HFL-DVR with independently controlled phases,” Power Electronics, IEEE Transactions on, vol. 27, pp. 1706–1718, April 2012.

[2]         S. Biswas, S. Goswami, and A. Chatterjee, “Optimal distributed generation placement in shunt capacitor compensated distribution systems considering voltage sag and harmonics distortions,” Generation, Transmission Distribution, IET, vol. 8, pp. 783–797, May 2014.

[3]         C. N. M. Ho and H. S. H. Chung, “Implementation and performance evaluation of a fast dynamic control scheme for capacitor-supported interline DVR,” IEEE Trans. Power Electron., vol. 25, pp. 1975 –1988, Aug. 2010.

[4]         J. Rosas-Caro, F. Mancilla-David, J. Ramirez-Arredondo, and A. Bakir, “Two-switch three-phase ac-link dynamic voltage restorer,” Power Electronics, IET, vol. 5, pp. 1754–1763, November 2012.

[5]         S. Subramanian and M. Mishra, “Interphase ac-ac topology for voltage sag supporter,” Power Electronics, IEEE Transactions on, vol. 25, pp. 514 –518, feb. 2010.

Design Considerations of a Fault Current Limiting Dynamic Voltage Restorer (FCL-DVR)

IEEE TRANSACTIONS ON SMART GRID, 2014

ABSTRACT

This paper proposes a new fault current limiting dynamic voltage restorer (FCL-DVR) concept. The new topology uses a crowbar bidirectional thyristor switch across the output terminals of a conventional back-to-back DVR. In the event of a load short, the DVR controller will deactivate the faulty phase of the DVR and activate its crowbar thyristor to insert the DVR filter reactor into the grid to limit the fault current. A fault condition is detected by sensing the load current and its rate of change. The FCL-DVR will operate with different protection strategies under different fault conditions. Design of the FCL-DVR involves selecting important parameters, such as DVR power rating, dc link voltage of the DVR, output filter reactors and capacitors, and grid-tied transformers is proposed. The design methodology of the proposed FCL-DVR is fully discussed based on power systems computer aided design (PSCAD)/electromagnetic transients including dc (EMTDC) simulation. A scaled-down experimental verification is also carried out. Both modeling and experimental results confirm the effectiveness of the new FCL-DVR concept for performing both voltage compensation and fault current limiting functions.

KEYWORDS:

1.      Dynamic voltage restorer (DVR)

2.      Fault current limiting (FCL)

3.      Parameter design method

4.      Voltage compensation

SOFTWARE: MATLAB/SIMULINK

CIRCUIT DIAGRAM:

Fig. 1 Topology of FCL-DVR.

  

EXPECTED SIMULATION RESULTS:

Fig 2. Simulation results of voltage compensation operation of FCL-DVR. Waveforms of grid voltages, PCC voltages, load currents FCL-DVR output voltages, and dc link voltages of the FCL-DVR during voltage fluctuation event and (b) unbalanced voltage event.

 Fig. 3 Simulation waveforms of grid voltages, PCC voltages, load currents, FCL-DVR output voltages, and FCL-DVR dc link voltages during (a) single-phase to ground, (b) phase-to-phase, (c) two-phase to ground, and (d) three-phase to ground short circuit fault.

 Fig. 4. Simulation results of fault current limiting and recovery processes of FCL-DVR. Simulation waveforms of the IGBT currents, thyristor currents, thyristor voltages, and dc link voltages of the FCL-DVR during (a) current limiting stage under a three-phase to ground short-circuit fault and (b) recovery stage after the three-phase to ground short-circuit fault is removed

CONCLUSION

A new FCL-DVR concept is proposed to deal with both voltage fluctuation and short current faults. The new topology uses a crowbar bidirectional thyristor switch across the output terminals of a conventional back-to-back DVR. In the event of load short, the DVR controller will deactivate the faulty phase of the DVR and activate its crowbar thyristor to insert the DVR filter reactor into the grid to limit the fault current. The FCL-DVR will operate with different protection strategies under different fault conditions. Based on theoretical analysis, PSCAD/EMTDC simulation and experimental study, we conclude the following.

1) With the crowbar bidirectional thyristor across the output terminal of the inverter, the proposed FCL-DVR can compensate voltage fluctuation and limit fault current.

2) The FCL-DVR can be used to deal with different types of short faults with minimum influence on nonfault phases. The FCL-DVR has the same power rating as a conventional DVR.

3) The delta-connection mode of the shunt transformers minimizes the influence of dc link voltage fluctuations and suppresses the 3rd harmonics.

4) The proposed control method can detect faults within two cycles.

5) The design methodology based on the analysis of the relationship between main circuit parameters and compensation capacity could be helpful to the design of FCL-DVR.

REFERENCES

[1]         Z. Shuai et al., “A dynamic hybrid var compensator and a two-level collaborative optimization compensation method,” IEEE Trans. Power Electron., vol. 24, no. 9, pp. 2091–2100, Sep. 2009.

[2]         L. Sainz, J. J. Mesas, R. Teodorescu, and P. Rodriguez, “Deterministic and stochastic study of wind farm harmonic currents,” IEEE Trans. Energy Convers., vol. 25, no. 4, pp. 1071–1080, Dec. 2010.

[3]         F. Boico and B. Lehman, “Multiple-input maximum power point tracking algorithm for solar panels with reduced sensing circuitry for portable applications,” Solar Energy, vol. 86, no. 1, pp. 463–475, Jan. 2012.

[4]         R. F. Arritt and R. C. Dugan, “Distribution system analysis and the future smart grid,” IEEE Trans. Ind. Appl., vol. 47, no. 6, pp. 2343–2350, Nov. 2011.

[5]         U. Supatti and F. Z. Peng, “Z-source inverter with grid connected for wind power system,” in Proc. Energy Convers. Congr. Expo. (ECCE), San Jose, CA, USA, 2009, pp. 398–403.

Design and Evaluation of a Mini-Size SMES Magnet for Hybrid Energy Storage Application in a kW-Class Dynamic Voltage Restorer

IEEE Transactions on Applied Superconductivity, 2017 

ABSTRACT

This paper presents the design and evaluation of a mini-size GdBCO magnet for hybrid energy storage (HES) application in a kW-class dynamic voltage restorer (DVR). The HES-based DVR concept integrates with one fast-response high power superconducting magnetic energy storage (SMES) unit and one low-cost high-capacity battery energy storage (BES) unit. Structural design, fabrication process and finite-element modeling (FEM) simulation of a 3.25 mH/240 A SMES magnet wound by state-of-the-art GdBCO tapes in SuNAM are presented. To avoid the internal soldering junctions and enhance the critical current of the magnet simultaneously, an improved continuous disk winding (CDW) method is proposed by introducing different gaps between adjacent single-pancake coil layers inside the magnet. About 4.41% increment in critical current and about 3.42% increment in energy storage capacity are demonstrated compared to a conventional CDW method. By integrating a 40 V/100 Ah valve-regulated lead-acid (VRLA) battery, the SMES magnet is applied to form a laboratory HES device for designing the kW-class DVR. For protecting a 380 V/5 kW sensitive load from 50% voltage sag, the SMES unit in the HES based scheme is demonstrated to avoid an initial discharge time delay of about 2.5 ms and a rushing discharging current of about 149.15 A in the sole BES based scheme, and the BES unit is more economically feasible than the sole SMES based scheme for extending the compensation time duration.

KEYWORDS:

1.      Superconducting magnetic energy storage (SMES)

2.      SMES magnet design

3.      Hybrid energy storage (HES),

4.      Battery energy storage (BES)

5.      Continuous disk winding (CDW)

6.      Dynamic voltage restorer (DVR)

7.      Voltage sag compensation.

SOFTWARE: MATLAB/SIMULINK

CIRCUIT DIAGRAM:

Fig. 1. Circuit topology of the HES-based DVR.

  

EXPECTED SIMULATION RESULTS:

Fig 2. Transient voltage curves: (a) Load voltage before compensation; (b) Compensation voltage from the DVR; (c) Load voltage after compensation.

Fig. 3. Transient current and power curves: (a) SMES coil current; (b) Output power from the SMES coil; (c) Output power from the whole DVR.

Fig. 4. Transient voltage curves: (a) Load voltage before compensation; (b) Compensation voltage from the DVR; (c) Load voltage after compensation.

Fig. 5. Transient current and power curves of the SMES and BES systems: (a) Operating current; (b) Output power.

CONCLUSION

The structural design, fabrication process and FEM simulation of a 3.25 mH/240 A SMES magnet wound by state-of-the-art GdBCO tapes have been presented in this paper. The FEM simulation results have proved the performance enhancements in both the critical current and energy storage capacity by using the improved CDW scheme. Such a mini-size SMES magnet having relatively high power and low energy storage capacity is further applied to combine with a 40 V/100 Ah VRLA battery for developing a laboratory HES device in a kW-class DVR. In a 5 Kw sensitive load applications case, voltage sag compensation characteristics of three different DVR schemes by using a sole SMES system, a sole BES system and a SMES-BES-based HES device have been discussed and compared. With the fast-response high-power SMES, the maximum output current from the BES system is reduced from about 149.15 A in the BES-based DVR to 62.5 A in the HES-based DVR, and the drawback from the initial discharge time delay caused by the inevitable energy conversion process is offset by integrating the SMES system. With the low-cost high-capacity BES, practical compensation time duration is extended from about 32 ms in the SMES-based DVR to a longer duration determined by the BES capacity. Therefore, the proposed HES concept integrated with fast-response high-power SMES unit and low-cost high-capacity BES unit can be well expected to apply in practical large-scale DVR developments and other similar SMES applications.

REFERENCES

[1]         Mohd. H. Ali, B. Wu, and R. A. Dougal, “An overview of SMES applications in power and energy systems,” IEEE Trans. Sustainable Energy, vol. 1, no. 1, pp. 38-47, 2010.

[2]         X. Y. Chen et al., “Integrated SMES technology for modern power system and future smart grid,” IEEE Trans. Appl. Supercond., vol. 24, no. 5, Oct. 2014, Art. ID 3801605.

[3]         IEEE Std 1159-2009, IEEE Recommended Practice for Monitoring Electric Power Quality, 2009.

[4]         X. H. Jiang et al., “A 150 kVA/0.3 MJ SMES voltage sag compensation system,” IEEE Trans. Appl. Supercond., vol. 15, no. 2, pp. 1903-1906, Jun. 2005.

[5]         S. Nagaya et al., “Field test results of the 5 MVA SMES system for bridging instantaneous voltage dips,” IEEE Trans. Appl. Supercond.,vol. 16, no. 2, pp. 632-635, Jun. 2006.

Comparison of Superconducting Fault Current Limiter and Dynamic Voltage Restorer for LVRT Improvement of High Penetration Micro-Grid

 IEEE Transactions on Applied Superconductivity, 2016

ABSTRACT

For a high penetration micro-grid, improving its low-voltage ride-through (LVRT) capability under some minor or temporary faults can contribute to reinforcing power support and reducing network instability. In this paper, the comparison of a superconducting fault current limiter (SFCL) and a dynamic voltage restorer (DVR) for LVRT capability enhancement of a 10 kV micro-grid is conducted. Concerning the micro-grid which includes distributed photovoltaic (PV) generation, energy storage and loads, the effects of the SFCL and the DVR are compared in detail, and related theoretical analysis, simulation study, and economical evaluation are carried out. From the demonstrated results, the suggested two devices can both assist the micro-grid to achieve the LVRT operation, but the economics of the DVR are weaker than the SFCL. Moreover, compared to the DVR, the SFCL enables the energy storage unit to offer better control effects in power stabilization. From technical and economic perspectives, the SFCL is a more preferable choice than the DVR.

KEYWORDS:

1.      Dynamic voltage restorer (DVR)

2.      Low-voltage ride-through (LVRT)

3.      Micro-grid

4.      Superconducting fault current limiter (SFCL)

5.      Techno-economic.

SOFTWARE: MATLAB/SIMULINK

BLOCK DIAGRAM:

Fig. 1. Configuration structure of the flux-coupling type SFCL.

EXPECTED SIMULATION RESULTS:

Fig 2. Three-phase PCC voltages under the short-circuit fault. (a) Without auxiliary, (b) with the SFCL and (c) with the DVR.

Fig. 3. Operation characteristics of the micro-grid under the short-circuit fault. (a) PCC current and (b) frequency fluctuation.

Fig. 4. Power characteristics of the micro-grid under the short-circuit fault. (a) Exchange power Pex, (b) DG total power PDG-total and (c) load power PLoad.

Fig. 5. Operation characteristics of the three DG units under the short-circuit fault. (a) DG1, (b) DG 2 and (c) DG3.

CONCLUSION

Based on the theoretical analysis, simulation study, and economic evaluation, this paper carries out the comparison of the SFCL and the DVR for enhancing the micro-grid’s LVRT capability, and the following conclusions can be obtained. 1) The SFCL and the DVR can both assist the micro-grid to meet the LVRT requirements. 2) Regardless of the full-compensation or non-full-compensation DVR, its total cost is more than the SFCL. Although the full-compensation DVR is able to offer better transient performance indexes, there may be a tradeoff between performance contribution and device cost. 3) Applying the SFCL enables the energy storage unit to offer better control effects in power stabilization. From technical and economic perspectives, the SFCL will be a more preferable choice than the DVR. In the near future, the detailed optimization design and experimental test of the SFCL will be conducted, and the results will be reported later.

REFERENCES

[1]   Baoquan Liu, Fang Zhuo, Yixin Zhu, and Hao Yi, “System Operation and Energy Management of a Renewable Energy-Based DC Micro-Grid for High Penetration Depth Application,” IEEE Trans. Smart Grid, vol. 6, no. 3, pp. 1147–1155, May 2015.

[2]   Feng Zheng, et al., “Transient Performance Improvement of Microgrid by a Resistive Superconducting Fault Current Limiter,” IEEE Trans. Appl. Supercond., vol. 25, no. 3, June 2015, Art. No. 5602305.

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[4]   Tinghuai Ma, Jinjuan Zhou, Meili Tang, et al. “Social network and tag sources based augmenting collaborative recommender system,” IEICE Trans. Inf. Syst., vol. 98, no. 4, pp. 902–910, April 2015.

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