ABSTRACT:
In this paper, by using a modular hybrid structure,
a new topology for symmetric multilevel inverters (MLI) with a small number of
semiconductors and low voltage stress across switches is proposed. Despite many
other topologies, this topology can inherently produce negative levels and zero
levels without using the H-bridge. The voltage stress across a particular
switch of the proposed MLI is inversely proportional to the number of the
switching of that switch in a voltage period. The proposed structure is based
on two types of module, that is, the f-module and the e-module. The e-module
uses a capacitive voltage divider to double the number of non-zero levels. The
voltages of the capacitors are approximately balanced without complex control
methods. The basic structure of the proposed topology is formed by connecting
the f-module and the e-module in series with each other, and the cascaded
topology is developed by cascading multiple f-modules with an e-module. To
investigate the proposed topology and proving its practicability, simulation
results with MATLAB/Simulink, investigation of the capacitor voltages, loss
calculations and experimental results are presented. A comparative study is
also performed to show the merit of the new multilevel inverter over other
topologies.
KEYWORDS:
1. New modular hybrid multilevel inverter
2. Low voltage stress
3. Reduced number of semiconductor
SOFTWARE:
MATLAB/SIMULINK
CONCLUSION:
In
this paper, a new, modular, symmetric topology with a reduced number of
semiconductors and low voltage stress across switches is proposed. Two modules
which make the proposed topology, i.e. the f-module and the e-module, is
described. Two novel topologies based on the mentioned modules are proposed and
the output voltages, as well as the voltages of the capacitors, are
investigated via simulation. The simulation results show that the average
values of the capacitor voltages are close together and their ripple factors
are acceptable. Besides, the sensitivity of the average value of the capacitor
voltages to load change is low and the proposed topology can balance the
capacitor voltages after faults. The comparison results of the proposed
topologies with other topologies in different fields shows that the proposed
topologies considerably reduced the number of semiconductors and voltage stress
of the switches. Finally, the feasibility of the proposed model is proved by
experimental results and the experimental results are in good agreement with
simulation results.
REFERENCES:
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