A Five Level Inverter Topology with Single DC Supply by Cascading a Flying Capacitor Inverter and an H-Bridge

ABSTRACT:

In this paper, a new three-phase, five-level inverter topology with a single-dc source is presented. The proposed topology is obtained by cascading a three-level flying capacitor inverter with a flying H-bridge power cell in each phase. This topology has redundant switching states for generating different pole voltages. By selecting appropriate switching states, the capacitor voltages can be balanced instantaneously (as compared to the fundamental) in any direction of the current, irrespective of the load power factor. Another important feature of this topology is that if any H-bridge fails, it can be bypassed and the configuration can still operate as a three-level inverter at its full power rating. This feature improves the reliability of the circuit. A 3-kW induction motor is run with the proposed topology for the full modulation range. The effectiveness of the capacitor balancing algorithm is tested for the full range of speed and during the sudden acceleration of the motor.

KEYWORDS:

1.      Flying capacitor (FC)

2.       H-bridge

3.       Induction motor drive

4.       Multilevel inverter

SOFTWARE: MATLAB/SIMULINK

 CIRCUIT DIAGRAM:

 Fig 1 Proposed three- phase power circuit formed by the connection of a three phase flying capacitor inverter with H-bridge in series

 EXPECTED SIMULATION RESULTS:

 Fig. 2. Phase voltage V_AN , phase current IA and capacitor voltage ripple for different modulation indexes for phase A: ∆VC 1 = 5 V/div; ∆VC 2 = 10 V/div; IA = 2 A/div. (a) 10 Hz with modulation index of 0.2 (V_{A N} = 50 V/div, time = 20 ms/div). (b) 20 Hz with modulation index of 0.4 (V_AN = 100 V/div, time =10 ms/div). (c) 30 Hz with modulation  index  of  0.6  (V_AN  = 100 V/div, time = 10 ms/div). (d) 40 Hz with modulation index of 0.8 (V_{A N} = 100 V/div, time = 5 ms/div).

Fig. 3. Pole voltage V_AO , phase current IA and capacitor voltage ripple for different modulation indexes for phase A: ∆VC 1 = 5 V/div; ∆VC 2 = 10 V/div; IA = 2 A/div. (a) 10 Hz with modulation index of 0.2 (V_AO = 50 V/div, time = 20 ms/div). (b) 20 Hz with modulation index of 0.4 (V_AO = 100 V/div, time = 10 ms/div). (c) 30 Hz with modulation index of 0.6 (V_AO = 100 V/div, and time = 10 ms/div). (d) 40 Hz with modulation index of 0.8 (V_AO = 100 V/div, time = 5 ms/div).

       

 Fig. 4. Rapid acceleration of motor from 10 to 40 Hz in 5.5 s. Capacitor voltage remains constant. V_AN (phase voltage): 200 V/div, IA (phase current): 2 A/div, VC 1 (VD C /2 capacitor DC voltage): 100 V/div, VC 2 (VD C /4 capacitor DC voltage): 100 V/div, and time scale: 1 s/div.

      Fig. 5.  Capacitor balancing operation. The balancing logic has been disabled at T1. C1 balancing has been enabled at T2 and C2 balancing has been en- abled at T3. V_AN (phase voltage): 200 V/div, IA  (phase current): 2 A/div, VC 1(VD C /2 capacitor DC voltage): 100 V/div, VC 2 (VD C /4 capacitor DC voltage): 100 V/div, and time scale: 2 s/div.

CONCLUSION:

In this paper, a new three-phase f ve-level inverter topology with a single-dc source has been proposed. This configuration is formed by cascading a three-level FC inverter and capacitor-fed H-bridges. The key advantages of this topology compared to the conventional topologies include reduced number of devices and simple control. An important feature of this inverter is the ability to balance the capacitor voltages irrespective of load power factor. Another advantage of this inverter is that if one of the H-bridge fails, it can operate as a three-level inverter at full power rating by bypassing the H-bridge. This feature of the inverter improves the reliability of the system The proposed configuration has been analyzed and experimentally verifie for various modulation indexes and frequencies by running a 3-kW squirrel cage induction motor in V/f  control mode, at no load. The working of the capacitor balancing algorithm has been tested. The stable operation of the inverter for various modulation indexes and stability of the inverter voltage levels during rapid acceleration have been validated  experimentally

REFERENCES:

[1] L. G. Franquelo, J. Rodriguez, J. I. Leon, S. Kouro, R. Portillo, M.A.M.  Prats,  “The  age  of multilevel  converters  arrives,”  IEEE  Ind.  Electron.  Magazine, vol. 2, no. 2, pp. 28–39, June.2008.

[2] S.  Kouro,  M.  Malinowski,  K.  Gopakumar,  J.  Pou,  L.  G.  Franquelo,  B.Wu, J. Rodriguez, M. A. Perez, and J. I. Leon, “Recent Advances and  Industrial  Applications  of  Multilevel  Converters,”  IEEE  Trans.  Ind.  Electron.,vol. 57, no. 8, pp. 2553–2580, Aug. 2010.

[3] A. Nabae,  I.  Takahashi,  and H. Akagi,  “A  new  neutral-point-clamped  PWM inverter,” IEEE Trans. Ind. Appl., vol. IA-17, no. 5, pp. 518–523,  Sep. 1981. 

[4] M. Marchesoni, M. Mazzucchelli, and S. Tenconi, “A non-conventional  power  converter  for  plasma  stabilization,”  in  Proc.  IEEE  19th  Annu.  Power  Electron.  Spec. Conf.  (PESC’88) Rec., Apr.  11–14,  vol.  1,  pp.  122–129.

[5] Z.  Du,  L.M.  Tolbert,  J.  N.  Chiasson,  B.  Ozpineci,  H.  Li,  and  A.  Q.  Huang,  “Hybrid  cascaded H-bridges multilevel motor drive  control  for  electric vehicles,” in Proc. IEEE 37th Power Electron. Spec. Conf., Jun.  18–22, 2006, pp. 1–6.

A Three Level Common Mode Voltage Eliminated Inverter with Single Dc Supply Using Flying Capacitor Inverter and Cascaded H-Bridge

ABSTRACT:

A three-level common-mode voltage eliminated inverter with single dc supply using flying capacitor inverter and cascaded H-bridge has been proposed in this paper. The three phase space vector polygon formed by this configuration and the polygon formed by the common-mode eliminated states have been discussed. The entire system is simulated in Simulink and the results are experimentally verified. This system has an advantage that if one of devices in the H-bridge fails, the system can still be operated as a normal three-level inverter at full power. This inverter has many other advantages like use of single dc supply, making it possible for a back-to-back grid-tied converter application, improved reliability, etc.

KEYWORDS:

1.      Common-mode voltage elimination

2.       Hybrid multilevel inverter

3.       Multilevel inverter

4.       Three-level inverter

 SOFTWARE: MATLAB/SIMULINK

 BLOCK DIAGRAM:

Fig 1 Power circuit for the proposed three level common mode voltage eliminated inverter

EXPECTED SIMULATION RESULTS:

Fig. 2. Simulation result for testing the capacitor balancing algorithm. VAO : pole voltage (100 V/div), IA : pole current (5  A/div)  VC 1 :  cap1-voltage (100 V/div), VC 2 : cap2 voltage (50 V/div), VC M : common-mode voltage (50 V/div), time: 500 ms/div.

Fig. 3. Steady-state performance at 10 Hz. VAO : pole voltage (100 V/div),  VA N : phase voltage (100 V/div), VN O : neutral point voltage (20 V/div), IA : phase current (2 A/div), time: 20 ms/div.

Fig. 4. Steady-state performance at 20 Hz. VAO : pole voltage (100 V/div), VA N : phase voltage (100 V/div), VN O : neutral point voltage (20 V/div), IA : phase current (2 A/div), time: 10 ms/div.

Fig. 5. Steady-state performance at 30 Hz. VAO : pole voltage (100 V/div), VA N : phase voltage (100 V/div), VN O : neutral point voltage (20 V/div), IA : phase current (2 A/div), time: 10 ms/div.

Fig. 6. Steady-state performance at 40 Hz. VAO : pole voltage (100 V/div), VA N : phase voltage (100 V/div), VN O : neutral point voltage (20 V/div), IA : phase current (2 A/div).

 CONCLUSION:

In this paper, a three-level common-mode voltage eliminated inverter with single dc supply using flyin capacitor inverter and cascaded H-bridge was proposed and studied. The operation and performance of the proposed inverter  is simulated  in Simulink with induction motor load. Various aspects of the inverter configuration such as the transients and the performance of the capacitor balancing algorithm, have been studied. The proposed inverter is implemented in hardware using IGBT- based inverters. A three-phase Y-connected induction motor is run with the proposed inverter and the performance of the drive is analyzed for both steady-state operation and transient operation during sudden acceleration. In all the cases, the inverter was able to give faithful reproduction of intended voltage levels with negligible capacitor voltage ripple and common mode, thereby improving the life of bearings. This configuration has various advantages like motor being connected in single-ended configuration use of reduced number of switches, use of single dc supply, etc. Also, this configuration has improved reliability.In case of failure of one of the devices in the H-bridge, the inverter can still be operated as a normal three-level inverter  at full power or a two-level common-mode voltage eliminated inverter at full power rating by bypassing the H-bridges, thereby improving the overall reliability of the system greatly.

REFERENCES:

[1] L. G. Franquelo, J. Rodriguez, J. I. Leon, S. Kouro, R. Portillo, M.A.M.  Prats,  “The  age  of multilevel  converters  arrives,”  IEEE  Ind.  Electron.  Magazine, vol. 2, no. 2, pp. 28–39, June.2008.

[2] S.  Kouro,  M.  Malinowski,  K.  Gopakumar,  J.  Pou,  L.  G.  Franquelo,  B.Wu, J. Rodriguez, M. A. Perez, and J. I. Leon, “Recent Advances and  Industrial  Applications  of  Multilevel  Converters,”  IEEE  Trans.  Ind.  Electron.,vol. 57, no. 8, pp. 2553–2580, Aug. 2010.

[3] A. Nabae,  I.  Takahashi,  and H. Akagi,  “A  new  neutral-point-clamped  PWM inverter,” IEEE Trans. Ind. Appl., vol. IA-17, no. 5, pp. 518–523,  Sep. 1981. 

[4] M. Marchesoni, M. Mazzucchelli, and S. Tenconi, “A non-conventional  power  converter  for  plasma  stabilization,”  in  Proc.  IEEE  19th  Annu.  Power  Electron.  Spec. Conf.  (PESC’88) Rec., Apr.  11–14,  vol.  1,  pp.  122–129.

[5] Z.  Du,  L.M.  Tolbert,  J.  N.  Chiasson,  B.  Ozpineci,  H.  Li,  and  A.  Q.  Huang,  “Hybrid  cascaded H-bridges multilevel motor drive  control  for  electric vehicles,” in Proc. IEEE 37th Power Electron. Spec. Conf., Jun.  18–22, 2006, pp. 1–6.

Common-Mode Voltage Eliminated Three-Level Inverter using a Three-Level Flying-Capacitor Inverter and Cascaded H-Bridge

ABSTRACT:

This paper proposes a new 3 level common mode voltage eliminated inverter using an inverter structure formed by cascading a H-Bridge with a three-level flying capacitor inverter. The three phase space vector polygon formed by this configuration and the polygon formed by the common-mode eliminated states have been discussed. The entire system is simulated in Simulink and the results are experimentally verified. This system has an advantage that if one of devices in the H- Bridge fails, the system can still be operated as a normal 3 level inverter mode at full power. This inverter has many advantages like use of single DC-supply, making it possible for a back to back grid-tied converter application, improved reliability etc.

KEYWORDS:

1.      Common mode voltage elimination

2.       Three level inverter

3.       Multi-level inverter

 SOFTWARE: MATLAB/SIMULINK

 CIRCUIT DIAGRAM:

        

    

Figure 1. Power circuit for the proposed three level common mode voltage eliminated inverter

EXPECTED SIMULATION RESULTS:

   

Figure.2.Simulation result for testing the capacitor balancing algorithm. V_AO:Pole Voltage(100V/div), I_A:Pole Current(5A/div) VC1:Cap1-Voltage(100V/div), VC2:Cap2-Voltage(50V/div) ,VCM: Common mode voltage(50V/div) Time: 500mS/div.

  

Figure 3. Steady state performance at 10 Hz. VAO: Pole Voltage(100V/div), VAN: Phase Voltage(100V/div), VNO: Neutral point voltage(20V/div)IA:Phase Current(2A/div) T:20mS/div.

Figure 4. Steady state performance at 20 Hz. VAO: Pole Voltage(100V/div), VAN: Phase Voltage(100V/div), VNO: Neutral point Voltage(20V/div)IA: Phase Current(2A/div) T:10mS/div.

                                                           

Figure 5. Steady state performance at 30 Hz. VAO: Pole Voltage(100V/div), V_AN: Phase Voltage(100V/div), VNO: Neutral point Voltage(20V/div)IA: Phase Current(2A/div) T:10mS/div.

                                                                                                    

Figure 6. Steady state performance at 40 Hz. VAO: Pole Voltage(100V/div), V_AN: Phase Voltage(100V/div), VNO: Neutral point (20V/div)IA: Phase Current(2A/div) T:5mS/div.

                                    

Figure 7. Steady state performance at 50 Hz. VAO: Pole Voltage(100V/div), V_AN: Phase Voltage(100V/div), VNO: Neutral point Voltage(200V/div)IA: Phase Current(2A/div) T:5mS/div.

                         

        

Figure 8. Steady State performance at 10 Hz. VAO: Pole Voltage(50V/div), VC1:C1(Vdc/2) Cap voltage(50V/div), VC2: C2-Cap Voltage(50V/div), IA: Phase Current(2A/div), T:10mS/div

                   

Figure 9. Steady State performance at 20 Hz.VAO: Pole Voltage(50V/div), VC1:C1-Cap voltage(50V/div), VC2: C2-Cap Voltage(50V/div), IA: Phase Current(2A/div), T:10mS/div

                              

Figure 10. Steady State performance at 30 Hz.VAO: Pole Voltage(100V/div), VC1:C1-Cap voltage(50V/div), VC2: C2-Cap Voltage(50V/div), IA: Phase Current(2A/div), T:10mS/div

                        

Figure 11. Steady State performance at 40 Hz.VAO: Pole Voltage(100V/div), VC1:C1-Cap voltage(50V/div), VC2: C2-Cap Voltage(50V/div), IA: Phase Current(2A/div), T:10mS/div

                            

Figure 12. Steady State performance at 50 Hz.VAO: Pole Voltage(100V/div), VC1:C1-Cap voltage(50V/div), VC2: C2-Cap Voltage(50V/div), IA: Phase Current(2A/div), T:10mS/div

                            

Figure 13. Acceleration Performance. V_AN: Phase Voltage(100V/div), VC2: C2-Cap Voltage Ripple (2V/div), V_CM: Neutral point voltage (10V/div), I_A: Phase Current(2A/div) T:500mS/div.

                                             

Figure 14. Capacitor Balancing Algorithm Test, V_C1: C1(Vdc/2)Cap voltage, V_C2: C2 (Vdc/4) Cap Voltage, V_CM: Common mode voltage (10V/div) I_A: Phase Current10A/div, T:500mS/div

CONCLUSION:

A three-level common-mode voltage eliminated inverter using five-level inverter formed by cascading a three-level flying capacitor inverter with a H-bridge, was proposed and analyzed. The same was simulated for an induction motor load in Simulink and implemented using IGBT inverter modules. The entire drive structure with the proposed inverter and a three phase Y-connected induction motor was experimentally verified for steady-state operation at various modulation indices. The transient performance during sudden acceleration was also verified. It may be observed that the common mode voltage is negligible even during the switching intervals of the converter. This results in negligible bearing currents and improved life of the bearing. This configuration has reduced number of switches compared to other similar configurations. Another advantage of this topology is the possibility of common-mode voltage elimination using single-ended configuration where the motor windings are fed only from one side. Also, this configuration uses a single DC-supply unlike many other topologies which require multiple isolated supplies. Another important feature of this topology is that if one of the devices in the H-bridge were to fail, the entire configuration could work as a normal three-level inverter at full rated capacity by bypassing the H-Bridge, thereby greatly improving the reliability of the overall system.

 REFERENCES:

[1] S. Kouro, M. Malinowski, K. Gopakumar, J. Pou, L. G. Franquelo, B.Wu, J. Rodriguez, M. A. Perez, and J. I. Leon, “Recent Advances and Industrial Applications of Multilevel Converters,” IEEE Trans. Ind. Electron.,vol. 57, no. 8, pp. 2553–2580, Aug. 2010.

[2] J. Rodriguez, S. Bernet, B. Wu, J. O. Pontt, and S. Kouro, “Multilevel voltage-source-converter topologies for industrial medium-voltage drives,” IEEE Trans. Ind. Electron., vol. 54, no. 6, pp. 2930–2945, Dec.2007.

[3] A. Nabae, I. Takahashi, and H. Akagi, “A new neutral-point-clamped PWM inverter,” IEEE Trans. Ind. Appl., vol. IA-17, no. 5, pp. 518–523, Sep. 1981.

[4] T. A. Meynard and H. Foch, “Multi-level conversion: High voltage choppers and voltage-source inverters,” in Proc. IEEE 23rd Annu. Power Electron.Spec. Conf., Jun. 29–Jul. 3, 1992, vol. 1, pp. 397–403.

[5] M. Marchesoni, M. Mazzucchelli, and S. Tenconi, “A non-conventional power converter for plasma stabilization,” in Proc. IEEE 19th Annu. Power Electron. Spec. Conf. (PESC’88) Rec., Apr. 11–14, vol. 1, pp. 122–129.