ABSTRACT:
This paper proposes a new 3 level common mode voltage
eliminated inverter using an inverter structure formed by cascading a H-Bridge
with a three-level flying capacitor inverter. The three phase space vector
polygon formed by this configuration and the polygon formed by the common-mode eliminated
states have been discussed. The entire system is simulated in Simulink and the
results are experimentally verified. This system has an advantage that if one
of devices in the H- Bridge fails, the system can still be operated as a normal
3 level inverter mode at full power. This inverter has many advantages like use
of single DC-supply, making it possible for a back to back grid-tied converter
application, improved reliability etc.
KEYWORDS:
1.
Common mode voltage elimination
2.
Three level inverter
3.
Multi-level inverter
SOFTWARE: MATLAB/SIMULINK
CIRCUIT DIAGRAM:
Figure 1. Power circuit for the proposed three level
common mode voltage eliminated inverter
EXPECTED SIMULATION RESULTS:
Figure.2.Simulation
result for testing the capacitor balancing algorithm. VAO:Pole
Voltage(100V/div), IA:Pole Current(5A/div)
VC1:Cap1-Voltage(100V/div), VC2:Cap2-Voltage(50V/div) ,VCM: Common mode
voltage(50V/div) Time: 500mS/div.
Figure
3. Steady state performance at 10 Hz. VAO: Pole Voltage(100V/div), VAN: Phase
Voltage(100V/div), VNO: Neutral point voltage(20V/div)IA:Phase Current(2A/div)
T:20mS/div.
Figure
4. Steady state performance at 20 Hz. VAO: Pole Voltage(100V/div), VAN: Phase
Voltage(100V/div), VNO: Neutral point Voltage(20V/div)IA: Phase Current(2A/div)
T:10mS/div.
Figure
5. Steady state performance at 30 Hz. VAO: Pole Voltage(100V/div), VAN:
Phase Voltage(100V/div), VNO: Neutral point Voltage(20V/div)IA: Phase
Current(2A/div) T:10mS/div.
Figure
6. Steady state performance at 40 Hz. VAO: Pole Voltage(100V/div), VAN:
Phase Voltage(100V/div), VNO: Neutral point (20V/div)IA: Phase Current(2A/div) T:5mS/div.
Figure
7. Steady state performance at 50 Hz. VAO: Pole Voltage(100V/div), VAN:
Phase Voltage(100V/div), VNO: Neutral point Voltage(200V/div)IA: Phase
Current(2A/div) T:5mS/div.
Figure
8. Steady State performance at 10 Hz. VAO: Pole Voltage(50V/div), VC1:C1(Vdc/2)
Cap voltage(50V/div), VC2: C2-Cap Voltage(50V/div), IA: Phase Current(2A/div),
T:10mS/div
Figure
9. Steady State performance at 20 Hz.VAO: Pole Voltage(50V/div), VC1:C1-Cap
voltage(50V/div), VC2: C2-Cap Voltage(50V/div), IA: Phase Current(2A/div),
T:10mS/div
Figure
10. Steady State performance at 30 Hz.VAO: Pole Voltage(100V/div), VC1:C1-Cap
voltage(50V/div), VC2: C2-Cap Voltage(50V/div), IA: Phase Current(2A/div),
T:10mS/div
Figure
11. Steady State performance at 40 Hz.VAO: Pole Voltage(100V/div), VC1:C1-Cap
voltage(50V/div), VC2: C2-Cap Voltage(50V/div), IA: Phase Current(2A/div),
T:10mS/div
Figure
12. Steady State performance at 50 Hz.VAO: Pole Voltage(100V/div), VC1:C1-Cap
voltage(50V/div), VC2: C2-Cap Voltage(50V/div), IA: Phase Current(2A/div),
T:10mS/div
Figure
13. Acceleration Performance. VAN: Phase Voltage(100V/div), VC2:
C2-Cap Voltage Ripple (2V/div), VCM: Neutral point voltage
(10V/div), IA: Phase Current(2A/div) T:500mS/div.
Figure
14. Capacitor Balancing Algorithm Test, VC1: C1(Vdc/2)Cap voltage, VC2:
C2 (Vdc/4) Cap Voltage, VCM: Common mode voltage (10V/div) IA:
Phase Current10A/div, T:500mS/div
CONCLUSION:
A
three-level common-mode voltage eliminated inverter using five-level inverter
formed by cascading a three-level flying capacitor inverter with a H-bridge,
was proposed and analyzed. The same was simulated for an induction motor load in
Simulink and implemented using IGBT inverter modules. The entire drive
structure with the proposed inverter and a three phase Y-connected induction
motor was experimentally verified for steady-state operation at various
modulation indices. The transient performance during sudden acceleration was
also verified. It may be observed that the common mode voltage is negligible
even during the switching intervals of the converter. This results in
negligible bearing currents and improved life of the bearing. This
configuration has reduced number of switches compared to other similar
configurations. Another advantage of this topology is the possibility of common-mode
voltage elimination using single-ended configuration where the motor windings
are fed only from one side. Also, this configuration uses a single DC-supply
unlike many other topologies which require multiple isolated supplies. Another
important feature of this topology is that if one of the devices in the
H-bridge were to fail, the entire configuration could work as a normal
three-level inverter at full rated capacity by bypassing the H-Bridge, thereby
greatly improving the reliability of the overall system.
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