ABSTRACT:
In the present paper, a novel topology for generating
a 17–level inverter using three-level flying capacitor inverter and cascaded
H-bridge modules with floating capacitors. The proposed circuit is analyzed and
various aspects of it are presented in the paper. This circuit is
experimentally verified and the results are shown. The stability of the
capacitor balancing algorithm has been verified during sudden acceleration.
This circuit has many pole voltage redundancies. This circuit has an advantage
of balancing all the capacitor voltages instantaneously by switching through
the redundancies. Another advantage of this topology is its ability to generate
all the 17 pole voltages from a single DC link which enables back to back
converter operation. Also, the proposed inverter can be operated at all load
power factors and modulation indices. Another advantage is, if one of the
H-bridges fail, the inverter can still be operated at full load with reduced
number of levels.
KEYWORDS:
1.
Seventeen
level inverter
2.
Multilevel inverter
3.
Flying
Capacitor
4.
Cascaded H-bridge
SOFTWARE: MATLAB/SIMULINK
CIRCUIT DIAGRAM:
Fig.1.
Proposed seventeen level inverter configuration formed by cascading three level
flying capacitor inverter with 3 H-bridges using a Single DC link.
EXPECTED SIMULATION RESULTS:
(a)
(b)
(c)
(d)
Fig.2:
Voltages of Capacitors C2, C3, C4 along
with the phase current IA
(a) 10Hz operation, VAC4: (100V/div), VAC3:
(10V/div), VAC2: (25V/div),IA:5A/div, Timescale: (20 mS/div).
(b) 20Hz operation, VAC4: (20V/div), VAC3:
(10V/div), VAC2: (25V/div),IA:2A/div, Timescale: 10mS/div
(c) 30Hz operation, VAC4: (20V/div), VAC3:
(10V/div), VAC2: (25V/div),IA:2A/div, Timescale: 10mS/div
(d) 40Hz operation, VAC4: (10V/div), VAC3:
(10V/div), VAC2: (100V/div), IA:2A/div,Timescale:5mS/div
(a)
(b)
(c)
(d)
Fig.3:
Voltages of Cap1 with Pole voltage VAO,
Phase A Voltage VAN and phase current
IA.
(a) 10Hz operation, VAC1( 50V/div), VAO: Pole
voltage( 100V/div),VAN: Phase Voltage (100V/div), IA: 2A/div, Timescale: (20mS/div).
(b) 20Hz operation, VAC1: ( 50V/div), VAO: Pole
voltage( 100V/div),VAN: Phase Voltage (100V/div), IA: 2A/div, Timescale: (10mS/div).
(c) 30Hz operation, VAC1: ( 50V/div), VAO: Pole
voltage( 100V/div), VAN: Phase Voltage (100V/div), IA: 2A/div, Timescale: (10mS/div).
(d) 40Hz operation, VAC1: ( 50V/div), VAO: Pole
voltage( 100V/div),VAN: Phase Voltage (100V/div), IA: 2A/div, Timescale: (10mS/div).
(a)
(b)
Fig.4. Performance of the capacitor balancing
algorithm during sudden acceleration at no load from 10Hz to 40Hz (a) VAC1:Cap AC1 voltage(100V/div), VAO: Pole
Voltage(100V/div) , VAN: Phase Voltage(100V/div), IA: Phase current(2A/div) (b) VAC4:Cap AC4 voltage(10V/div), VAC3:Cap
AC3 voltage (20V/div), VAC2:Cap AC2 voltage (20V/div), IA: Phase
current(2A/div)
CONCLUSION:
A seventeen
level inverter formed
by cascading a
three level flying capacitor
with floating capacitor
H-bridges has been proposed. The
proposed inverter has reduced number of switches as compared with standard configurations. The inverter has
other advantages like
ability to balance
all the capacitor voltages at all load currents and power factors
there by generating
seventeen pole voltages
with very little distortion.
Another advantage of the
inverter is ability to generate all the
required voltage levels
using a single
DC link. This possibility
of using single
DC link enables
back to back converter operation
where a front
end can be
used so that power can
be drawn and
supplied to grid
at desired power 1%#'
factor. Another important advantage is if one of devices in one of H-bridges
fail, the inverter can still be operated at full load at reduced number of
levels. The proposed inverter
is analyzed and
its performance is experimentally verified
for various modulation
indices and load
currents by running
a three phase
3kW squirrel cage induction motor.
The stability of
the capacitor balancing algorithm
has been tested
experimentally by suddenly accelerating
the motor at no load
and observing the capacitor voltages at various load currents.
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