Seventeen-Level Inverter
Formed by Cascading Flying Capacitor and Floating Capacitor H-Bridges
ABSTRACT:
A multilevel inverter for generating 17 voltage
levels using a three-level flying capacitor inverter and cascaded H-bridge modules
with floating capacitors has been proposed. Various aspects of the proposed
inverter like capacitor voltage balancing have been presented in the present
paper. Experimental results are presented to study the performance of the
proposed converter. The stability of the capacitor balancing algorithm has been
verified both during transients and steady-state operation. All the capacitors in
this circuit can be balanced instantaneously by using one of the pole voltage
combinations. Another advantage of this topology is its ability to generate all
the voltages from a single dc-link power supply which enables back-to-back
operation of converter.
Also, the proposed inverter can be operated at all
load power factors and modulation indices. Additional advantage is, if one of
the H-bridges fail, the inverter can still be operated at full load with reduced
number of levels. This configuration has very low dv/dt and common-mode voltage
variation.
KEYWORDS:
1. Cascaded H-bridge
2. Flying capacitor
3. Multilevel inverter
4. 17-level inverter
SOFTWARE: MATLAB/SIMULINK
BLOCK DIAGRAM:
Fig. 1. Block diagram of controller for
one phase of the proposed converter.
EXPECTED SIMULATION RESULTS:
Fig. 2. Pole, Phase, capacitor voltages along
with current for 10-Hz operation of converter. VAC1(50 V/div),VAO: Pole voltage
(100 V/div), VAN: Phase Voltage (100 V/div), VAC4: (100 V/div),VAC3: (10
V/div),VAC2: (25 V/div), IA:2 A/div, Timescale: (20 mS/div).
Fig.3.
Pole, Phase, capacitor voltages along with current for 20-Hz operation of the
converter. VAC1: (50 V/div),VAO: Pole voltage(100 V/div), VAN: Phase Voltage
(100 V/div), VAC4: (20 V/div),VAC3: (10 V/div),VAC2: (25 V/div), IA:2 A/div,
Timescale: 10 mS/div.
Fig.4.
Pole, Phase, capacitor voltages along with current for 30-Hz operation of the
converter. VAC1:(50 V/div),VAO: Pole voltage(100 V/div),VAN: Phase Voltage (100
V/div), VAC4: (20 V/div),VAC3: (10 V/div),VAC2: (25 V/div), IA:2 A/div,
Timescale: 10 mS/div.
Fig.
5. Pole, Phase, capacitor voltages along with current for 40-Hz operation of
the converter. VAC1:(50 V/div),VAO: Pole voltage(100 V/div),VAN: Phase Voltage
(100 V/div), VAC4: (10 V/div),VAC3: (10 V/div),VAC2: (100 V/div), IA:2 A/div,
Timescale: 5 mS/div.
Fig.
6. Pole, Phase, capacitor voltages along with current during sudden
acceleration. VAC1:Cap AC1 voltage(100 V/div), VAO: Pole Voltage(100 V/div), VAN:
Phase Voltage(100 V/div),VAC4:Cap AC4 voltage(10 V/div), VAC3:Cap AC3 voltage
(20 V/div), VAC2:Cap AC2 voltage (20 V/div),IA: Phase current (2 A/div)
Timescale: 500 mS/div.
CONCLUSION:
A
new 17-level inverter configuration formed by cascading a three-level flying
capacitor and three floating capacitor H-bridges has been proposed for the
first time. The voltages of each of the capacitors are controlled
instantaneously in few switching cycles at all loads and power factors
obtaining high performance output voltages and currents. The proposed
configuration uses a single dc link and derives the other voltage levels from
it. This enables back-to-back converter operation where power can be drawn and
supplied to the grid at prescribed power factor. Also, the proposed 17-level
inverter has improved reliability. In case of failure of one of the H-bridges,
the inverter can still be operated with reduced number of levels supplying full
power to the load. This feature enables it to be used in critical applications like
marine propulsion and traction where reliability is of highest concern. Another
advantage of the proposed configuration is modularity and symmetry in structure
which enables the inverter to be extended to more number of phases like
five-phase and six-phase configurations with the same control scheme. The proposed
inverter is analyzed and its performance is experimentally verified for various
modulation indices and load currents by running a three-phase 3-kW squirrel
cage induction motor. The stability of the capacitor balancing algorithm has
been tested experimentally by suddenly accelerating the motor at no load and
observing the capacitor voltages at various load currents.
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