A 15-Level Asymmetric Cascaded H Bridge Multilevel Inverter with Less Number of Switches For Photo Voltaic System

ABSTRACT

This Paper presents a 15 level Asymmetrical Cascaded H bridge multilevel inverter Topology for Photovoltaic system. In this system Symmetrical and Asymmetrical Multilevel inverter (MLI) is utilized. In Symmetrical MLI, the DC source magnitude are equal ie., 50Vdc, 50Vdc & 50Vdc., where as in Asymmetrical MLI the DC source Magnitude are unequal and it is designed with binary form of voltage such as 50Vdc, 100Vdc & 200Vdc.Comparing both the MLI , Asymmetrical MLI generates a number of output voltage level with same number of Power semiconductor switches. The phase Disposition Pulse Width Modulation (PD-PWM) technique is used for controlling the Power semiconductor switches in MLI. The results are verified in both MATLAB and PROTEUS.

 KEYWORDS

1.      Photo voltaic system(PV)

2.      Symmetrical MLI

3.      Asymmetrical MLI

4.       PD-PWM

5.      PIC16F877A

6.      IR112

SOFTWARE: MATLAB/SIMULINK

CONCLUSION

A symmetrical Cascaded H bridge Multil level inverter(SCHBMLI) and Asymmetrical Cascaded H bridge Multilevel Inverer(ASCHBMLI) has been analysed in this paper. Both the Inverter consist of the same power semiconductor switches but the output voltage levels are different. In SCHBMLI the ouput voltage is 9 level , while ASCHBMLI the ouput voltage levels are 15 level. The THD analysis for ACHBMLI using the switching technique of high switching frequency (2KHz) PD-PWM is 6.03% and the switching technique of low switching frequency(50Hz) is 10.26%. In this system the THD is very less by using PDPWM technique.This type of system is used for high power applications for photovoltaic system bec it reduce the overall cost and size of the system

REFERENCES

[1] G. Eason, B. Noble, and I.N. Sneddon, “On certain integrals of Javier pereda, and juan dixon, “cascaded multilevel converters: optimal asymmetries and floating capacitor control” ieee transactions on industrial electronics, vol. 60, no. 11, november 2013.

[2] M. Mohamad fathi mohamad elias, nasrudin abd. Rahim, hew wooi ping, and mohammad nasir uddin, asymmetrical cascaded multilevel inverter based on transistor-clamped h-bridge power cell ieee transactions on industry applications, vol. 50, no. 6, november/december 2014.

[3] Eduardo e. Espinosa, jose r. Espinoza, pedro e. Melín, roberto o. Ramírez, felipe villarroel,javier a. Muñoz, member, and luis morán, fellow, ieeea new modulation method for a 13-level asymmetric inverter toward minimum thd ieee transactions on industry applications, vol. 50, no. 3, may/june 2014.

[4] Giampaolo buticchi, member, davide barater, emilio lorenzani, member, carlo concari and giovanni franceschini a nine-level grid-connected converter topology for single-phase transformerless pv systems ieee transactions on industrial electronics, vol. 61, no. 8, august 2014.

[5] Javier pereda, student member, ieee, and juan dixon, senior member,high-frequency link: a solution for using only one dc source in asymmetric cascaded multilevel inverters ieee ieee transactions on industrial electronics, vol. 58, no. 9, september 2011.

Overview and Comparison of Modulation and Control Strategies for Non-Resonant Single-Phase Dual-Active-Bridge dc-dc Converter

ABSTRACT:

 The non-resonant single-phase dual-active-bridge (NSDAB) dc-dc converter has been increasingly adopted for isolated dc-dc power conversion systems. Over the past few years, significant research has been carried out to address the technical challenges associated with modulations and controls of NSDAB dc-dc converter. The aim of this paper is to review and compare these recent state-of-the-art modulation and control strategies. Firstly, the modulation strategies for NSDAB dc-dc converter are analyzed. All possible phase-shift patterns are demonstrated, and the correlation analysis of the typical phases-shift modulation methods for NSDAB dc-dc converter is presented. Then, an overview of steady-state efficiency optimization strategies is discussed for NSDAB dc-dc converter. Moreover, a review of optimized techniques for dynamic responses is also provided. For both the efficiency and dynamic optimizations, thorough comparisons and recommendations are provided in this paper. Finally, to improve both steady state and transient performances, a combination approach to optimize both efficiency and dynamics for NSDAB dc-dc converter based on the reviewed methods is presented in this paper.

KEYWORDS:

1.      DAB converter

2.      Power Losses

3.      Current Stress

4.      Reactive Power

5.      Efficiency

6.      Power Control

7.      Current Feedback Control

8.      Observer-Based Control

9.      Dynamic Performances

SOFTWARE: MATLAB/SIMULINK

CONCLUSION:

NSDAB dc-dc converter has become one of the most attractive isolated dc-dc power conversion topologies for DC grid, solid-state transformer, automotive application, energy storage system and aerospace application. This paper offers a comprehensive overview of modulation methods, efficiency-optimization schemes and dynamic-optimization strategies of NSDAB dc-dc converter, and thorough comparisons of different optimization methods are conducted:

1). The typical modulation methods including the advanced phase-shift modulation and the variable frequency modulation methods are presented in this paper. Based on all possible eighteen phase-shift modulation patterns, the reason why SPS, DPS, EPS and TPS modulation schemes are selected for NSDAB dc-dc converter is analyzed. Moreover, the correlation analysis of typical phase-shift modulation methods including SPS, DSP, EPS and TPS modulation methods is illustrated, which can explain why the TPS modulation method can always provide the best efficiency for NSDAB dc-dc converter.

2). An overview of efficiency optimization schemes for NSDAB dc-dc converter including power-loss-model-based optimization methods, nonactive power optimization techniques, inductance current optimization strategies, ZVS range optimization schemes and burst mode are conducted. Under the consideration of both optimized performance and feasibility, the minimum-current-stress-optimized strategy with simple operation is recommended.

3). The paper also provides an overview of dynamic optimization strategies for NSDAB dc-dc converter including load-current feedforward schemes, direct-inductance-current control strategies and power-based control methods. When NSDAB dc-dc converter is connected to resistive load, the virtual-direct-power control scheme and the current sensorless control strategy are recommended because of excellent dynamic responses. When NSDAB dc-dc converter is connected to dc voltage bus, the asymmetric double-side modulation and the predictive current-mode control for fast transient response of required inductance current are recommended.

4). Finally, the paper presents an idea of hybrid efficiency-and dynamic-optimization concept to improve both steady state and transient performances of NSDAB dc-dc converter. A static and dynamic optimization strategy by combining minimum-current-stress strategy and power-control concept verifies the feasibility of the presented idea.

REFERENCES:

[1]R. W. De Doncker, D. M. Divan and M. H. Kheraluwala, "A three-phase soft-switched high power density DC/DC converter for high power applications,"Conference Record of the 1988 IEEE Industry Applications Society Annual Meeting, Pittsburgh, PA, USA, 1988, pp. 796-805 vol.1.

[2]R. W. A. A. De Doncker, D. M. Divan and M. H. Kheraluwala, "A three-phase soft-switched high-power-density DC/DC converter for high-power applications," inIEEE Transactions on Industry Applications, vol. 27, no. 1, pp. 63-73, Jan.-Feb. 1991.

[3]H. Akagi, S. Kinouchi and Y. Miyazaki, "Bidirectional isolated dual-active-bridge (DAB) DC-DC converters using 1.2-kV 400-A SiC-MOSFET dual modules," inCPSS Transactions on Power Electronics and Applications, vol. 1, no. 1, pp. 33-40, Dec. 2016.

[4]B. Zhao, Q. Song, W. Liu and Y. Xiao, "Next-Generation Multi-Functional Modular Intelligent UPS Systemfor Smart Grid," inIEEE Transactions on Industrial Electronics, vol. 60, no. 9, pp. 3602-3618, Sept. 2013.

[5]H. Wen, W. Xiao and B. Su, "Nonactive Power Loss Minimization in a Bidirectional Isolated DC-DC Converter for Distributed Power Systems," inIEEE Transactions on Industrial Electronics, vol. 61, no. 12, pp. 6822-6831, Dec. 2014. 

Novel Symmetric Modular Hybrid Multilevel Inverter with Reduced Number of Semiconductors and Low Voltage Stress across Switches

ABSTRACT:

In this paper, by using a modular hybrid structure, a new topology for symmetric multilevel inverters (MLI) with a small number of semiconductors and low voltage stress across switches is proposed. Despite many other topologies, this topology can inherently produce negative levels and zero levels without using the H-bridge. The voltage stress across a particular switch of the proposed MLI is inversely proportional to the number of the switching of that switch in a voltage period. The proposed structure is based on two types of module, that is, the f-module and the e-module. The e-module uses a capacitive voltage divider to double the number of non-zero levels. The voltages of the capacitors are approximately balanced without complex control methods. The basic structure of the proposed topology is formed by connecting the f-module and the e-module in series with each other, and the cascaded topology is developed by cascading multiple f-modules with an e-module. To investigate the proposed topology and proving its practicability, simulation results with MATLAB/Simulink, investigation of the capacitor voltages, loss calculations and experimental results are presented. A comparative study is also performed to show the merit of the new multilevel inverter over other topologies.

KEYWORDS:

1.      New modular hybrid multilevel inverter

2.      Low voltage stress

3.      Reduced number of semiconductor

SOFTWARE: MATLAB/SIMULINK

CONCLUSION:

In this paper, a new, modular, symmetric topology with a reduced number of semiconductors and low voltage stress across switches is proposed. Two modules which make the proposed topology, i.e. the f-module and the e-module, is described. Two novel topologies based on the mentioned modules are proposed and the output voltages, as well as the voltages of the capacitors, are investigated via simulation. The simulation results show that the average values of the capacitor voltages are close together and their ripple factors are acceptable. Besides, the sensitivity of the average value of the capacitor voltages to load change is low and the proposed topology can balance the capacitor voltages after faults. The comparison results of the proposed topologies with other topologies in different fields shows that the proposed topologies considerably reduced the number of semiconductors and voltage stress of the switches. Finally, the feasibility of the proposed model is proved by experimental results and the experimental results are in good agreement with simulation results.

REFERENCES:

[1] N. A. Rahim, K. Chaniago, and J. Selvaraj, “Single-phase seven-level grid-connected inverter for photovoltaic system”, IEEE Trans. Ind. Electron., vol. 58, no. 6, pp. 2435–2443, Jun. 2011.

[2] K. Bandara, T. Sweet, and J. Ekanayake, “Photovoltaic applications for off-grid electrification using novel multi-level inverter technology with energy storage”, Renew. Energy, vol. 37, no. 1, pp. 82–88, Jan. 2012.

[3] J. Chavarria, D. Biel, F. Guinjoan, C. Meza, and J. J. Negroni, “Energy balance control of PV cascaded multilevel grid-connected inverters under level-shifted and phase-shifted PWMs”, IEEE Trans. Ind. Electron., vol. 60, no. 1, pp. 98–111, Jan. 2013.

[4] Muhammad H. Rashid ,” Multilevel Power Converters”, in Power electronics handbook : devices, circuits, and applications handbook 3rd ed., Elsevier, 2011, pp. 455-456

[5] J. Rodriguez, J. S. Lai, and F. Z. Peng, “Multilevel inverters: A survey of topologies, controls, and applications”, IEEE Trans. Ind. Electron., vol. 49, no. 4, pp. 724–738, Aug. 2002. 

Design and Implementation of Seventeen Level Inverter With Reduced Components

ABSTRACT:

The multilevel inverters (MLI) are resourceful in producing a voltage waveform with superior-quality staircase counterfeit sinusoidal and depressed harmonic distortion (THD). Several conventional topologies are proposed to realize the MLI however, the limitations of these topologies may involve more DC sources and power-switching devices, and less THD, which in turn, increases the cost and size of the inverter. These drawbacks can be eliminated with the proposed hybrid Cascaded H-Bridge Multilevel Inverter with reduced components topology. As compared with the established MLI topologies the recommended topology having a reduced number of DC sources, power-switching devices, component count level factor, lesser TSV, more efficient, lesser THD, and cost-effective. The proposed MLI is a blend of a single-phase T-Type inverter and an H-Bridge module made of sub switches. This article incorporates the design and simulation of the multilevel inverter with staircase PWM technique. Further, the 9-level and 17-level MLI is examined with different combinational loads. The proposed inverter is stable during nonlinear loads, and it is well suited for FACTS and renewable energy grid-connected applications. An operational guideline has been explained with correct Figures and tables. The Output voltage wave is realized in numerical simulation. Finally, the experimental demonstrations were performed by implementing a hardware prototype setup for both linear and nonlinear loads using the dSPACE controller laboratory.

KEYWORDS:

1.      Hybrid cascaded H-bridge multilevel inverter with reduced components

2.       Pulse width modulation (PWM)

3.      Total harmonics distortion (THD)

SOFTWARE: MATLAB/SIMULINK

CONCLUSION:

In this article, a hybrid Cascaded H-Bridge Multilevel Inverter with reduced components topology was presented. The proposed basic MLI builds a voltage with nine levels and extended to seventeen levels by cascading. This topology uses lesser power switches that reduce the price and volume of the inverter and improves efficiency. The proposed inverter requires relatively less power electronic components to generate the desired output than other similar topologies. Comparative analysis shows that the proposed topology has a superior cost factor per level. In the output, the proposed inverter's harmonic content is comparatively less than similar Cascaded H-Bridge MLI for both linear and nonlinear loads with nearly more efficiency _. The proposed inverter is stable during nonlinear loads, and it is well suited for FACTS and renewable energy grid-connected applications. To authenticate the proposed inverter satisfactory simulation is done in MATLAB/Simulink. The experimental setup is assembled in the laboratory confirmations unique with more significant output voltage levels, having lower harmonic content and reduced power switches, and greater efficiency. Subsequently proposed inverter appears some encouraging properties when compared with various similar topologies.

REFERENCES:

[1] P. Omer, J. Kumar, and B. S. Surjan, ``A review on reduced switch count multilevel inverter topologies,'' IEEE Access, vol. 8, pp. 22281_22302, 2020.

[2] C. Dhanamjayulu, S. R. Khasim, S. Padmanaban, G. Arunkumar, J. B. Holm-Nielsen, and F. Blaabjerg, ``Design and implementation of multilevel inverters for fuel cell energy conversion system,'' IEEE Access, vol. 8, pp. 183690_183707, 2020, doi: 10.1109/ACCESS.2020.3029153.

[3] C. Dhanamjayulu and S. Meikandasivam, ``Implementation and comparison of symmetric and asymmetric multilevel inverters for dynamic loads,'' IEEE Access, vol. 6, pp. 738_746, 2018.

[4] C. Dhanamjayulu and S. Meikandasivam, ``Performance veri_cation of symmetric hybridized cascaded multilevel inverter with reduced number of switches,'' in Proc. Innov. Power Adv. Comput. Technol. (i-PACT), Vellore, India, Apr. 2017, pp. 1_5.

[5] M. D. Siddique, S. Mekhilef, N. M. Shah, A. Sarwar, A. Iqbal, and M. A. Memon, ``A new multilevel inverter topology with reduce switch count,'' IEEE Access, vol. 7, pp. 58584_58594, 2019.

A Variable DC Link based Novel Multilevel Inverter Topology for Low Voltage Applications

ABSTRACT:

In this paper; a variable dc link based novel multilevel inverter (MLI) topology is proposed. This proposed topology comprises two variable dc links and a modified H-bridge unit. This new single-phase topology offers advantages such as reduction in count of switches; gate drivers and dc sources while simultaneously improving the power quality. The proposed topology has been analyzed for both symmetric and asymmetric modes of operation. A comparative study of the proposed topology with some recent MLI topologies has been presented. The comparative study indicates that the proposed topology requires less number of dc sources; switches and driver circuits as compared to other topologies. The proposed topology has been simulated for 31- level asymmetric configuration in MATLAB/SIMULINK environment to verify the proper operation of proposed topology. Harmonic analysis was also performed for 31-level inverter which showed significant reduction in the total harmonic distortion (THD) for phase voltage and current waveforms. The proposed topology is suitable for low voltage applications such as standalone photovoltaic (PV) systems and hybrid electric vehicles (HEVs).

KEYWORDS:

1.      Multilevel Inverter

2.      Asymmetric Configuration

3.       Variable DC Link

4.      Reduced Device Count

SOFTWARE: MATLAB/SIMULINK

 CONCLUSION:

In this paper; a novel MLI topology having two variable dc links and a modified H-bridge unit has been proposed for low voltage applications. Generalized form of proposed topology was explained for both symmetric and asymmetric modes of operation from the perspective of quantitative parameters. Through various comparisons made between the proposed asymmetric topology and other reduced device count topologies; it is concluded that the proposed topology requires less number of dc sources; switches and gate drivers as compared with the other presented topologies in literature. However total PIV in proposed topology is found to be slightly higher as compared with the ACHE topology. On the basis of chosen performance indices; proposed topology is found to be more economical as compared to their counterparts. Performance of 31-level proposed asymmetric topology was shown by simulated voltage and current waveforms. Since the switches T5 and T6 in the modified H-bridge have to withstand the total output voltage of MLI; these two switches must be of high voltage rating and hence the proposed topology is best suited for LV applications. The proposed topology also has a distinctive feature of utilizing asymmetric dc sources in a manner to maintain nearly even blocking voltage stress across the switches (TJ to T4) in a modified H-bridge. This feature reduces the number of variety of switches significantly. Harmonic analysis results showed the significant reduction of harmonics in voltage and current waveforms. So there is no need of filter circuit to eliminate harmonics. The proposed topology will be beneficial in LV applications such as standalone PV systems; hybrid electric vehicles (EVs) etc. due to its various benefits. In future; hardware implementation of the proposed topology will be done.

REFERENCES:

[I] L.M. Tolbert; F-Z. Peng and T.G. HabetIer; "Multilevel converters for large electric drives," IEEE Trans. Ind. AppL; vol. 35; no. I; pp. 36-44; Jan.lFeb. 1999.

[2] J. Rodriguez; S. Bernet; B. Wu; J.O. Pontt and S. Kouro,"Multilevel voltage-source-converter topologies for industrial medium-voltage drives," IEEE Trans. Ind. Electron.; vol. 54; no. 6; pp. 2930-2945;Dec. 2007.

[3] J. Rodriguez; J.S. Lai and FL Peng; "Multilevel inverters: A survey of topologies; controls and applications," IEEE Trans. Ind. Electron.; vol. 49; no. 4; pp. 724-738; Aug. 2002.

[4] I. Colak; E. Kabalci and R. Bayindir; "Review of multilevel voltage source inverter topologies and control schemes," Energy Converso Manag.; vol. 52; no. 2; pp. 1114- 1128; 2011.

[5] M. Malinowski; K. Gopakumar; J. Rodriguez and M.A. Perez; "A survey on cascaded multilevel inverters," IEEE Trans. Ind. Electron.; vol. 57; no. 7;p p. 2197-2206; July 20I O. 

A Simplified Space Vector Pulse-Width Modulation Scheme for Three-Phase Cascaded H-bridge Inverters

ABSTRACT:

A simplified space vector pulse-width modulation (SVPWM) for three-phase cascaded H-bridge (CHB) inverters is presented in this paper. Treating each unit as a three-level inverter and adopting serial calculation mode, a CHB inverter is modulated unit by unit using three-level SVPWM. Duty cycles of real sector are obtained by mapping duty cycles of sector 1, in which the calculation of three-level SVPWM is done. The process to implement multilevel SVPWM is simplified to the process to implement three-level SVPWM. By reusing FPGA chip resource which is used for the calculation of three-level SVPWM, the presented SVPWM can be easily adopted to a CHB inverter with different number of units, while the FPGA chip resource utilization is reduced significantly. In addition, the presented SVPWM provides an effective switching frequency higher than the switching frequency of IGBTs. Simulation and experimental results are provided to verify the feasibility of the presented SVPWM.

KEYWORDS:

1.      Three-phase CHB multilevel inverter

2.       Space vector modulation (SVM)

3.      Space vector pulse-width modulation (SVPWM)

4.      Field programmable gate array (FPGA)

 SOFTWARE: MATLAB/SIMULINK

 CONCLUSION:

This paper presents a simplified SVPWM scheme for three-phase CHB inverters. Treating each unit as a three-level inverter and adopting serial calculation mode, a three-phase CHB inverter with n units is modulated unit by unit by using three-level SVPWM instead of using multilevel SVPWM. Then, duty cycles of sector N used to generate gate pulses are obtained by mapping duty cycles of sector 1. Based on principles of the presented SVPWM, the tedious process to implement the conventional multilevel SVPWM is simplified significantly. By reusing FPGA chip resources which are used to do the calculation of three-level SVPWM, the presented SVPWM can be easily adopted to a three-phase CHB inverter with different number of units. Simulation and experimental results are used to validate the presented SVPWM. The presented SVPWM provides a higher effective switching frequency of nfs, while maintains the same dc-link voltage utilization as that of the conventional SVPWM. Compared with the conventional SVPWM, FPGA chip resource utilization of the presented SVPWM is reduced significantly, while the FPGA resource utilization increment of the presented SVPWM is controlled without dramatically increasing.

REFERENCES:

[1] A. Marquez, J. I. Leon, R. Portillo, S. Vazquez, L. G. Franquelo, and S. Kouro, “Adaptive phase-shifted PWM for multilevel cascaded H-bridge converters for balanced or unbalanced operation,” IECON Conf. IEEE Ind. Electron. Society, Yokohama, Japan, Nov. 2015, pp. 5124-5129.

[2] J. Rodriguez, L. G. Franquelo, S. Kouro, J. I. Leon, R. C. Portillo, M. A. M. Prats, and M. A. Perez, “Multilevel Converters: An Enabling Technology for High-Power Applications,” Proc. IEEE, vol. 97, no.11, pp. 1786-1817, Dec. 2009.

[3] H. Abu-Rub, J. Holtz, J. Rodriguez, and G. Baoming, “Medium-Voltage Multilevel Converters—State of the Art, Challenges, and Requirements in Industrial Applications,” IEEE Trans. Ind. Electron., vol. 57, no. 8, pp.2581-2596, Aug. 2010.

[4] C. Lee, B. Wang, S. Chen, S. Chou, J. Huang, P. Cheng, H. Akagi, and P. Barbosa., “Average Power Balancing Control of a STATCOM Based on the Cascaded H-Bridge PWM Converter with Star Configuration,” IEEE Trans. Ind. Appl., vol. 50, no. 6, pp. 3893-3901, Jun. 2014.

[5] S. Essakiappan, H. S. Krishnamoorthy, P. Enjeti, R. S. Balog, and S. Ahmed, “Multilevel Medium-Frequency Link Inverter for Utility Scale Photovoltaic Integration,” IEEE Trans. Power Electron., vol. 30, no.7, pp. 3674-3684, Jul. 2015.

A New Family of Step-up Hybrid Switched-Capacitor Integrated Multilevel InverterTopologies with Dual Input Voltage Sources

ABSTRACT:

In the low voltage based renewable systems like PV and Fuel cell applications, the step-up of the output voltage to drive the loads is essential. For this, the integration of switched-capacitor (SC) units with the dc-ac converters will have the potential advantages like improved efficiency, optimal switching devices, small size of passive elements (L and C) as compared with traditional two-stage conversion system (dc/dc converter and dc/ac converter). This paper focuses on a new family of step-up multilevel inverter topologies with switched capacitor integration with dual input voltage sources. With the flexibility of 2 dc sources and switching capacitor circuits, four different topologies have been suggested in this paper with features of high voltage gain, reduced component count, reduced voltage stress and self-voltage balancing of the capacitor while achieving a higher number of levels. A detailed analysis of proposed multilevel inverters has been analyzed with the symmetrical and asymmetrical mode of operations and the associated gain, the number of levels, and other performance indices are presented. An in-depth study of all the topologies has been accomplished in this paper with several comparative studies in terms of components count, voltage gain and cost. The effectiveness and practicability of the suggested topology with 13 level output voltage has been explained by the experimental results obtained from a scale down prototype.

KEYWORDS:

1.      Hybrid Reduced Switch Bidirectional Cascaded H-Bridge Multilevel Inverter

2.      Pulse Width Modulation (PWM)

3.      Total Harmonics Distortion (THD)

SOFTWARE: MATLAB/SIMULINK

CONCLUSION:

In this paper, a new family of dual input-driven multilevel inverters with the integration of switched-capacitor units for attaining the boost capability as well as multilevel voltage has been discussed. For this, various multilevel inverters have been analyzed with the symmetrical/asymmetrical dc sources as well as different switched capacitor arrangements, and the detailed pros and cons of all configurations are presented. The higher voltage level generation, step-up operation, and lower voltage stress of the switches have been the main features of the proposed topologies. The comparative analysis is provided to highlight the benefits of the proposed topologies over the various multilevel inverters present in the literature. To show the effectiveness of the proposed topologies, a laboratory prototype of PT-I with the symmetrical sources is designed in the laboratory which will produce 13 levels and associated experimental results are provided. Different real-time operating conditions (like a step change in load, power factor, MI, and frequency) have been tested with the proposed topology and the experimental results show good agreement with the simulation results.

REFERENCES:

[1] B. P. Reddy, M. Rao A, M. Sahoo and S. Keerthipati, "A Fault- Tolerant Multilevel Inverter for Improving the Performance of a Pole–Phase Modulated Nine-Phase Induction Motor Drive," IEEE Transactions on Industrial Electronics, vol. 65, no. 2, pp. 1107-1116, Feb. 2018

[2] M. Rawa et al., “Dual input switched-capacitor-based single phase hybrid boost multilevel inverter topology with reduced number of components,” IET Power Electron., vol. 13, no. 4, pp. 881–891, 2020.

[3] P. R. Bana, K. P. Panda, R. T. Naayagi, P. Siano, and G. Panda, “Recently Developed Reduced Switch Multilevel Inverter for Renewable Energy Integration and Drives Application: Topologies, Comprehensive Analysis and Comparative Evaluation,” IEEE Access, vol. 7, pp. 54888–54909, 2019.

[4] J. S. Jagabar and V. Krishnaswamy, “An assessment of recent multilevel inverter topologies with reduced power electronics components for renewable applications,” Renewable and Sustainable Energy Reviews, vol. 82. Elsevier Ltd, pp. 3379– 3399, 01-Feb-2018.

[5] B. P. Reddy and S. Keerthipati, "A Multilevel Inverter Configuration for an Open-End-Winding Pole-Phase-Modulated- Multiphase Induction Motor Drive Using Dual Inverter Principle," IEEE Trans. on Ind. Electron, vol. 65, no. 4, pp. 3035- 3044, April 2018.