ABSTRACT
A conventional asymmetrical half-bridge (AHB) converter
is one of the most promising topologies in low-to-medium power applications
because of zero-voltage switching (ZVS) of all switches and small number of
components. However, when the converter is designed taking a hold-up time into
consideration, it has a large DC offset current in a transformer and a small
transformer turns-ratio. To solve these problems, a new AHB converter with an
integrated boost converter is proposed in this letter. Because the
proposed converter compensates for the hold-up time using the integrated boost
converter without additional loss in the nominal state, it can achieve the
optimized efficiency regardless of the hold-up time. The effectiveness and
feasibility are verified with a 250-400V input and 45V/3.3A output prototype.
KEYWORDS:
1.
Hold-up
time
2.
DC/DC
converter
3.
Asymmetrical
half-bridge converter
4.
High
efficiency.1
SOFTWARE: MATLAB/SIMULINK
CIRCUIT
DIAGRAM:
Fig.
1. The conventional AHB converters. (a) DCS HB converter and (b)
boost-cascaded AHB converter.
Fig. 2. The proposed converter.
EXPECTED EXPERIMENTAL RESULTS:
Fig.3.
Waveforms of the prototype converters with 400v input,3.3A/45v output
(a) The conventional AHB converter and (b) the
proposed converter
Fig.4.Transient
operation during the hold-up time
Fig.5.
Measured Efficiency
CONCLUSION
In
this letter, a boost-integrated AHB converter is proposed. The proposed
converter integrates a boost converter in the rectifier in a new manner.
Because the proposed converter can obtain an additional voltage gain during a
hold-up time, it can be designed optimally in the nominal state regardless of
the hold-up time requirement. Furthermore, since the proposed converter does
not cause an additional loss in the nominal state, it can achieve the optimized
efficiency.
REFERENCES
[1] .J.
K. Han, J. W. Kim, Y. Jang, B. Kang, J. Choi, and G. W. Moon, “Efficiency
Optimized Asymmetric Half-Bridge Converter with Hold-Up Time Compensation,” in
Proc. IEEE Power Electron. Conf., pp.2254-2261, May, 2016.
[2] H.
Wu, T. Mu, X. Gao, and Y. Xing, “A Secondary-Side Phase-Shift-Controlled LLC
Resonant Converter With Reduced Conduction Loss at Normal Operation for Hold-Up
Time Compensation Application," IEEE Trans. Power Electron., vol.
30, no. 10, pp. 5352-5357, Oct. 2015.
[3] Y.
S. Lai, Z. J. Su, and W. S. Chen, “New Hybrid Control Technique to Improve
Light Load Efficiency While Meeting the Hold-Up Time Requirement for Two-Stage
Server Power,” IEEE Trans. Power Electron., vol. 29, no. 9, pp.
4763-4775, Sep. 2014.
[4] D.
K. Kim, S. Moon, C. O. Yeon, G. W. Moon, “High-Efficiency LLC Resonant
Converter With High Voltage Gain Using an Auxiliary LC Resonant Circuit,” IEEE
Trans. Power Electron., vol. 31, no. 10, pp. 6901-6909, Oct. 2016
[5] J.
B. Lee, J. K. Kim, J. H. Kim, J. I. Baek, and G. W. Moon, “A High-Efficiency
PFM Half-Bridge Converter Utilizing a Half-Bridge LLC Converter Under Light
Load Conditions,” IEEE Trans. Power Electron., vol. 30, no. 9, pp.
4931-4942, Sep. 2015
