ABSTRACT:
In
this paper, a unusual switching technique is implemented using a fuzzy logic
approach. The proposed technique simplifies the conventional method by
eliminating the traditional logic gate design. The fuzzy logic pulse generator acts
as a look-up table as well as a pulse generator. Based on the modulation index
as input, controlled membership functions (MFs) and rules of the fuzzy logic
controller (FLC) opens various possibilities in producing pulses directly. The
proposed technique is evaluated on the cascaded multilevel inverter with
symmetric and asymmetric operations using selective harmonic elimination pulse
width modulation (SHE-PWM). MFs are designed based on the pre-calculated firing
conditions for different modulation index values. The hardware verification is
carried out to support the proposed switching technique.
KEYWORDS:
1. Cascaded
H-Bridge Multilevel Inverter (CHBMLI)
2. Fuzzy
Logic Controller (FLC)
3. Membership
Function (MF)
4. Pulse
Width Modulation (PWM)
5. Selective
Harmonic Elimination (SHE)
SOFTWARE:
MATLAB/SIMULINK
BLOCK DIAGRAM:
Fig.
1. (a) Symmetrical 7-level CHB MLI and (b) Trinary asymmetrical
9-level
CHB MLI.
Fig.
2. (a) Output voltage and load current waveforms for 7 level symmetric CHB MLI
at mi = 0:3, (b) Output voltage and load current waveforms for 7 level symmetric CHB MLI at mi = 0:6, (c)
Output voltage and load current
waveforms for 7 level symmetric CHB MLI at mi = 0:9, (d) Output voltage and load
current waveforms for 9 level asymmetric CHB MLI at mi = 0:9, (e) THD spectrum of 7 level output
voltage waveform at mi = 0.9 for
symmetrical CHB MLI, (f) THD profile of symmetrical CHB MLI for both simulation
and experimental at different mi values.
CONCLUSION:
An
unusual switching approach is introduced for avoiding look-up table and complex
logic gate arrangements to generate the gating pulses for the CHB MLI. In the
proposed technique, single FLC works as a pulse generating lookup table which provides
gate pules without any mediator. Furthermore, the proposed technique is
experimentally validated with symmetrical and asymmetrical CHB MLI for seven
and nine level configurations respectively. The proposed technique can be extended
to n-level inverters and other MLI configurations.
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[1]
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