Design and Hardware Implementation Considerations of Modified Multilevel Cascaded H-Bridge Inverter for Photovoltaic System

 ABSTRACT:  

 Inverters are an essential part in many applications including photovoltaic generation. With the increasing penetration of renewable energy sources, the drive for efficient inverters is gaining more and more momentum. In this work, output power quality, power loss, implementation complexity, cost, and relative advantages of the popular cascaded multilevel H-bridge inverter, and a modified version of it are explored. Optimal number of levels, and the optimal switching frequency for such inverters are investigated, and a 5-level architecture is chosen considering the trade-offs. This inverter is driven by level shifted in-phase disposition pulse width modulation technique to reduce harmonics, which is chosen through deliberate testing of other advanced disposition pulse width modulation techniques. To reduce the harmonics further, the application of filters is investigated, and an LC filter is applied which provided appreciable results. This system is tested in MATLAB/Simulink, and then implemented in hardware after design and testing in Proteus ISIS. The general cascaded multilevel H-bridge inverter design is also implemented in hardware to demonstrate a novel low-cost MOSFET driver build for this study. The hardware setups use MOSFETs as switching devices and low-cost ATmega microcontrollers for generating the switching pulses via level shifted in-phase disposition pulse width modulation. This implementation substantiated the effectiveness of the proposed design.

 KEYWORDS:                                                               

 

1.      Inverter

2.      Multilevel Inverter

3.      Cascaded H-Bridge

4.      Modified Cascaded H-Bridge

5.      Advanced PWM Techniques

6.      MOSFET Driving Technique

7.      Level Shifted In-Phase Disposition Pulse Width Modulation

 

SOFTWARE: MATLAB/SIMULINK

CIRCUIT DIAGRAM:

 

FIGURE 1. (a) General structure of multilevel inverter. Each 4-switch block represents an H-bridge, each equipped with its own DC source. (b) Modified 5 level inverter configuration: this one uses 6 switches instead of the 8 required in the general structure.

 

EXPERIMENTAL RESULTS:

FIGURE 2. Outputs of 5-level general and modified CHB at 2 kHz switching frequency. The general CHB signal quality is better than the modified CHB signal quality because of the presence of non-linearity in the modified design.

 

FIGURE 3. Outputs of 5-level general and modified CHB at 6 kHz switching frequency. The general CHB signal quality is better than the modified CHB signal quality because of the presence of non-linearity in the modified design.

(a)

(b)

FIGURE 4. (a) The filtered and unfiltered output voltage of the modified CHB for 4 kHz PWM switching frequency, and (b) the filtered output current of the modified CHB for 4 kHz PWM switching frequency.

CONCLUSION:

In this work, a single phase modified 5-level symmetric cascaded multilevel H-bridge (CHB) inverter with 6 switches has been presented. This reduction in switches has reduced the cost, complexity, area requirement, and losses, while improving efficiency. The CHB architecture has been chosen over other designs because of its unique advantages. These benefits of CHB- namely, the optimum number of levels in the CHB, and the optimum switching frequency – have been investigated thoroughly. A 7-level CHB with 6 kHz switching frequency has appeared as the best performing system in this study. However, this performance has been achieved for unfiltered outputs. In this paper, an LC filter has been used to reduce THD in the output significantly. When this filter is used, both 5-level and 7-level CHBs have demonstrated almost equal THD levels. Thus the less complex, and hence more practical, 5-level design has been chosen. Also, advanced PWM techniques have been investigated to determine their effectiveness in reducing the THD, and level shifted in-phase disposition PWM technique has been selected to be used in the proposed system as it has provided the best performance. Because of the use of PWM switching, the switching frequency has also been much higher than 7 kHz – which has increased the switching losses, but the resulting reduction in THD has immensely improved the inverter performance. As a result, the increased switching losses can be safely neglected. After obtaining satisfactory simulation results in MATLAB/Simulink, this system has been designed and tested in Proteus for hardware implementation, and then implemented in hardware using MOSFETs and ATmega microcontrollers. The hardware outputs have deviated a bit from the simulation results, and the use of transformers to aid in measurement has been identified as the reason. A use-case of the proposed inverter has also been presented. Future expansion of this work can focus on applying this design in real-life standalone and/or grid-connected PV system.

 REFERENCES:

[1] K. Sano and M. Takasaki, "A transformerless D-STATCOM based on a multivoltage cascade converter requiring no DC sources," IEEE transactions on power electronics, vol. 27, pp. 2783-2795, 2012.

[2] B. Gultekin and M. Ermis, "Cascaded multilevel converter-based transmission STATCOM: System design methodology and development of a 12 kV±12 MVAr power stage," IEEE transactions on power electronics, vol. 28, pp. 4930-4950, 2013.

[3] H. Abu-Rub, J. Holtz, J. Rodriguez, and G. Baoming, "Medium-voltage multilevel converters—State of the art, challenges, and requirements in industrial applications," IEEE Transactions on Industrial Electronics, vol. 57, pp. 2581-2596, 2010.

[4] A. Balikci and E. Akpinar, "A multilevel converter with reduced number of switches in STATCOM for load balancing," Electric Power Systems Research, vol. 123, pp. 164-173, 2015.

[5] J. S. Lee, H. W. Sim, J. Kim, and K. B. Lee, "Combination Analysis and Switching Method of a Cascaded H-Bridge Multilevel Inverter Based on Transformers With the Different Turns Ratio for Increasing the Voltage Level," IEEE Transactions on Industrial Electronics, vol. 65, pp. 4454-4465, 2018.