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Tuesday, 15 December 2020

Design and Simulation of Single-Phase Five-Level Symmetrical Cascaded H-Bridge Multilevel Inverter with Reduces Number of Switches

ABSTRACT:  

Multilevel inverter is an effective and practical solution for increasing power demand and reducing harmonics of ac waveforms. Such inverters synthesize a desired output voltage from several levels of dc voltages as inputs. This paper analyzes the performance of five level cascaded H-bridge multilevel inverter with reduce number of power switches. Further by reducing switches and increasing level will reduce filter cost & harmonic content. 5- Level cascaded H-bridge asymmetrical multilevel inverter topology requires 8 switches but in this new multilevel inverter it requires 6 switches in which same multilevel is obtained. Invariably switching losses and cost also reduced. In this paper only multilevel inverter circuitry will be studied. The performance has been analyzed by the MATLAB/Simulink.

KEYWORDS:

1.      Cascaded multilevel inverter

2.      SPWM

3.      APOD

4.      PD

5.      POD

6.      THD

 

SOFTWARE: MATLAB/SIMULINK

 BLOCK DIAGRAM:



Figure 1: Multi-user Distributed Massive MIMO transceiver model system.

 

CIRCUIT DIAGRAM:

 


Figure 2: Circuit diagram of 5-level CHB MLI with reduced switches & dc sources.

 

EXPERIMENTAL RESULTS:

 


Figure 3: 5-levels THD in MATLAB tool.

CONCLUSION:

This paper showed that this modified multilevel inverter topology with reduced number of switches can be implemented for industrial drive applications. This multilevel inverter structure and its basic operations have been analyzed. A detailed procedure for calculating required voltage level on each stage has been analyzed. As conventional five-level inverter involves eight switches, it increases switching losses; cost and circuit complexity. This 5-level inverter engages only six switches which reduces switching losses, cost and circuit complexity. Moreover it effectively reduces lower order harmonics. Therefore effective reduction of total harmonics distortion is achieved.

 REFERENCES:

1. http://www.esru.strath.ac.uk

2. Kavita M, Arunkumar A, Gokulnath N, Arun S (2012) New cascaded H-bridge multilevel inverter topology with reduced number of switches and sources. IOSR-JEEE 2: 26-36.

3. Peng FZ, Lai JS (2003) Multilevel converters, A new breed of power Electronics converters. IEEE Trans Ind Appl 32: 509 -517.

4. Rodriguez J, Lai JS, Peng FZ (2003) Multilevel Inverter: A survey topology control and application. IEEE Trans Ind Electro 49: 724-738.

5. Nabae A, Takahashi I, Akagi H (2003) New neutral point clamped pwm inverter. IEEE Trans Ind Appl IA-17: 518-523.