Design and Hardware Implementation Considerations of Modified Multilevel Cascaded H-Bridge Inverter for Photovoltaic System

 ABSTRACT:  

 Inverters are an essential part in many applications including photovoltaic generation. With the increasing penetration of renewable energy sources, the drive for efficient inverters is gaining more and more momentum. In this work, output power quality, power loss, implementation complexity, cost, and relative advantages of the popular cascaded multilevel H-bridge inverter, and a modified version of it are explored. Optimal number of levels, and the optimal switching frequency for such inverters are investigated, and a 5-level architecture is chosen considering the trade-offs. This inverter is driven by level shifted in-phase disposition pulse width modulation technique to reduce harmonics, which is chosen through deliberate testing of other advanced disposition pulse width modulation techniques. To reduce the harmonics further, the application of filters is investigated, and an LC filter is applied which provided appreciable results. This system is tested in MATLAB/Simulink, and then implemented in hardware after design and testing in Proteus ISIS. The general cascaded multilevel H-bridge inverter design is also implemented in hardware to demonstrate a novel low-cost MOSFET driver build for this study. The hardware setups use MOSFETs as switching devices and low-cost ATmega microcontrollers for generating the switching pulses via level shifted in-phase disposition pulse width modulation. This implementation substantiated the effectiveness of the proposed design.

 KEYWORDS:                                                               

 

1.      Inverter

2.      Multilevel Inverter

3.      Cascaded H-Bridge

4.      Modified Cascaded H-Bridge

5.      Advanced PWM Techniques

6.      MOSFET Driving Technique

7.      Level Shifted In-Phase Disposition Pulse Width Modulation

 

SOFTWARE: MATLAB/SIMULINK

CIRCUIT DIAGRAM:

 

FIGURE 1. (a) General structure of multilevel inverter. Each 4-switch block represents an H-bridge, each equipped with its own DC source. (b) Modified 5 level inverter configuration: this one uses 6 switches instead of the 8 required in the general structure.

 

EXPERIMENTAL RESULTS:

FIGURE 2. Outputs of 5-level general and modified CHB at 2 kHz switching frequency. The general CHB signal quality is better than the modified CHB signal quality because of the presence of non-linearity in the modified design.

 

FIGURE 3. Outputs of 5-level general and modified CHB at 6 kHz switching frequency. The general CHB signal quality is better than the modified CHB signal quality because of the presence of non-linearity in the modified design.

(a)

(b)

FIGURE 4. (a) The filtered and unfiltered output voltage of the modified CHB for 4 kHz PWM switching frequency, and (b) the filtered output current of the modified CHB for 4 kHz PWM switching frequency.

CONCLUSION:

In this work, a single phase modified 5-level symmetric cascaded multilevel H-bridge (CHB) inverter with 6 switches has been presented. This reduction in switches has reduced the cost, complexity, area requirement, and losses, while improving efficiency. The CHB architecture has been chosen over other designs because of its unique advantages. These benefits of CHB- namely, the optimum number of levels in the CHB, and the optimum switching frequency – have been investigated thoroughly. A 7-level CHB with 6 kHz switching frequency has appeared as the best performing system in this study. However, this performance has been achieved for unfiltered outputs. In this paper, an LC filter has been used to reduce THD in the output significantly. When this filter is used, both 5-level and 7-level CHBs have demonstrated almost equal THD levels. Thus the less complex, and hence more practical, 5-level design has been chosen. Also, advanced PWM techniques have been investigated to determine their effectiveness in reducing the THD, and level shifted in-phase disposition PWM technique has been selected to be used in the proposed system as it has provided the best performance. Because of the use of PWM switching, the switching frequency has also been much higher than 7 kHz – which has increased the switching losses, but the resulting reduction in THD has immensely improved the inverter performance. As a result, the increased switching losses can be safely neglected. After obtaining satisfactory simulation results in MATLAB/Simulink, this system has been designed and tested in Proteus for hardware implementation, and then implemented in hardware using MOSFETs and ATmega microcontrollers. The hardware outputs have deviated a bit from the simulation results, and the use of transformers to aid in measurement has been identified as the reason. A use-case of the proposed inverter has also been presented. Future expansion of this work can focus on applying this design in real-life standalone and/or grid-connected PV system.

 REFERENCES:

[1] K. Sano and M. Takasaki, "A transformerless D-STATCOM based on a multivoltage cascade converter requiring no DC sources," IEEE transactions on power electronics, vol. 27, pp. 2783-2795, 2012.

[2] B. Gultekin and M. Ermis, "Cascaded multilevel converter-based transmission STATCOM: System design methodology and development of a 12 kV±12 MVAr power stage," IEEE transactions on power electronics, vol. 28, pp. 4930-4950, 2013.

[3] H. Abu-Rub, J. Holtz, J. Rodriguez, and G. Baoming, "Medium-voltage multilevel converters—State of the art, challenges, and requirements in industrial applications," IEEE Transactions on Industrial Electronics, vol. 57, pp. 2581-2596, 2010.

[4] A. Balikci and E. Akpinar, "A multilevel converter with reduced number of switches in STATCOM for load balancing," Electric Power Systems Research, vol. 123, pp. 164-173, 2015.

[5] J. S. Lee, H. W. Sim, J. Kim, and K. B. Lee, "Combination Analysis and Switching Method of a Cascaded H-Bridge Multilevel Inverter Based on Transformers With the Different Turns Ratio for Increasing the Voltage Level," IEEE Transactions on Industrial Electronics, vol. 65, pp. 4454-4465, 2018.

Design and Simulation of Single-Phase Five-Level Symmetrical Cascaded H-Bridge Multilevel Inverter with Reduces Number of Switches

ABSTRACT:  

Multilevel inverter is an effective and practical solution for increasing power demand and reducing harmonics of ac waveforms. Such inverters synthesize a desired output voltage from several levels of dc voltages as inputs. This paper analyzes the performance of five level cascaded H-bridge multilevel inverter with reduce number of power switches. Further by reducing switches and increasing level will reduce filter cost & harmonic content. 5- Level cascaded H-bridge asymmetrical multilevel inverter topology requires 8 switches but in this new multilevel inverter it requires 6 switches in which same multilevel is obtained. Invariably switching losses and cost also reduced. In this paper only multilevel inverter circuitry will be studied. The performance has been analyzed by the MATLAB/Simulink.

KEYWORDS:

1.      Cascaded multilevel inverter

2.      SPWM

3.      APOD

4.      PD

5.      POD

6.      THD

 

SOFTWARE: MATLAB/SIMULINK

 BLOCK DIAGRAM:

Figure 1: Multi-user Distributed Massive MIMO transceiver model system.

 

CIRCUIT DIAGRAM:

 

Figure 2: Circuit diagram of 5-level CHB MLI with reduced switches & dc sources.

 

EXPERIMENTAL RESULTS:

 

Figure 3: 5-levels THD in MATLAB tool.

CONCLUSION:

This paper showed that this modified multilevel inverter topology with reduced number of switches can be implemented for industrial drive applications. This multilevel inverter structure and its basic operations have been analyzed. A detailed procedure for calculating required voltage level on each stage has been analyzed. As conventional five-level inverter involves eight switches, it increases switching losses; cost and circuit complexity. This 5-level inverter engages only six switches which reduces switching losses, cost and circuit complexity. Moreover it effectively reduces lower order harmonics. Therefore effective reduction of total harmonics distortion is achieved.

 REFERENCES:

1. http://www.esru.strath.ac.uk

2. Kavita M, Arunkumar A, Gokulnath N, Arun S (2012) New cascaded H-bridge multilevel inverter topology with reduced number of switches and sources. IOSR-JEEE 2: 26-36.

3. Peng FZ, Lai JS (2003) Multilevel converters, A new breed of power Electronics converters. IEEE Trans Ind Appl 32: 509 -517.

4. Rodriguez J, Lai JS, Peng FZ (2003) Multilevel Inverter: A survey topology control and application. IEEE Trans Ind Electro 49: 724-738.

5. Nabae A, Takahashi I, Akagi H (2003) New neutral point clamped pwm inverter. IEEE Trans Ind Appl IA-17: 518-523.

 

Single Phase 21 Level Asymmetric Cascaded Multilevel Inverter With Reduced Number Of Switches And Dc Sources

ABSTRACT:  

Multilevel inverter technology has emerged as a very important alternative in the field of medium and high power industrial drive applications. The emergence of multilevel inverters has been increasing since three decades. These new types of converters are suitable for high voltage and high power application due to their ability to synthesize waveforms with better harmonic spectrum. Several multilevel converter topologies have been developed; i) diode clamped, ii) flying capacitors, and iii) cascaded or H-bridge. Cascade Multilevel Inverter (CMI) is one of the productive topology from multilevel family. By increasing the number of output voltage levels in multilevel inverter the Total Harmonic Distortion (THD) can be minimized. This project proposes a new topology of 21 level asymmetric cascaded multilevel inverter with 11 unidirectional switches and 3 diodes and 4 DC voltages sources. Several Pulse Width Modulation techniques are available, among them Level shifting SPWM techniques such as PO, POD and Space Vector PWM are used and comparison is shown on the basis of THDs obtained. MATLAB/ SIMULINK software is used for simulation

 

SOFTWARE: MATLAB/SIMULINK

 BLOCK DIAGRAM:

Fig.1. Basic Block Diagram of Proposed Multilevel Inverter

CIRCUIT DIAGRAM:

Fig. 2. Proposed topology

EXPERIMENTAL RESULTS:

Fig.3. Simulation result of 21 level multilevel inverter using PD PWM     

                                      Fig. 4. Simulation result of 21 level multilevel inverter using POD PWM

 

  

Fig. 5. Simulation result of 21 level multilevel inverter   using SVPWM                                                                               

                                                                                    

                      

Fig. .6. Simulation result of Pulses of   Switches in PD PWM

 

Fig. 7.. Simulation result of Pulses of Switches in POD PWM

CONCLUSION:

In this project, a new topology for 21 levels is proposed with reduced number of switches and DC sources. The Proposed circuit is validated on MATLAB/Simulink platform. The simulation of the 21 level asymmetric cascaded multilevel inverter is successfully done using Space vector, Phase disposition and Phase Opposition disposition pulse width modulation techniques. Thus, this new circuit will require lesser hardware space, lesser cost; also the complexity of the circuit will reduce. From the FFT analysis, it is found that PD PWM and POD PWM techniques give least THD. It is observed that even after the reduction in switches and sources, the desired output is obtained.

 

REFERENCES:

[1]             Jannu Ramu, S.J.V. Prakash, K. Satya Srinivasu, R.N.D. Pattabhi Ram, M. Vishnu Prasad and Md. Mazhar Hussain,” Comparison Between Symmetrical And Asymmetrical Single Phase Seven Level Cascade H-Bridge Multilevel Inverter With PWM Topology,” International Journal of Multidisciplinary Sciences and Engineering, Vol . 3, no. 4, April 2012.

[2]             R.Karthikeyan, Dr.S.Chenthur Pandian,” An Efficient Multilevel Inverter System For Reducing THD With Space Vector Modulation,” International Journal of Computer Applications (0975 – 8887),Volume 23– No.2, June 2011.

[3]             Xiaodong Yang, Chonglin Wang, Liping Shi ,Zhenglong Xia,” Generalized Space Vector Pulse Width Modulation Technique For Cascaded Multilevel Inverters,” International Journal of Control and Automation, Vol.7, No.1 (2014), pp.11-26

[4]             Balamurugan M.,Gnana Prakash M.,Umashankar S.,” A New Seven Level Symmetric Inverter With Reduced Number Of Switches And Dc Sources,” Advances in Electrical Engineering (ICAEE), 2014 International Conference.

[5]             Elyas Zamiri.,Sajjad Hamkari.,Ebrahim Babaei.,” A New Cascaded Multilevel Inverter Structure With Less Number Of Switches,” 5th Power Electronics, Drive systems and Technologies Conference, 2014 .

 

 

Design of a New Combined Cascaded Multilevel Inverter Based on Developed H-Bridge with Reduced Number of IGBTs and DC Voltage Sources

 ABSTRACT:  

In this paper, a new combined cascaded multilevel inverter with reduced number of switches and DC voltage sources which is formed by series connection of same units with developed H-Bridge is proposed. For the purpose of generating all even and odd voltage levels 5 algorithms to determine the magnitudes of DC voltage sources is proposed. In order to investigate the advantages and disadvantages of the proposed combined cascaded multilevel inverter the proposed algorithms are compared to presented topologies from different points of view. The experimental results of the proposed topology are stated to check and verifying the performance of the proposed topology.

 

KEYWORDS:

1.      Multilevel inverter

2.      Cascaded multilevel inverter

3.      Combined topology

4.      Developed H-Bridge

 

SOFTWARE: MATLAB/SIMULINK

 

 CIRCUIT DIAGRAM:

                                               Fig. 1. Topology of proposed combined cascaded multilevel inverter.

 EXPERIMENTAL RESULTS:

 

 

(a)

 

(b)

 

(c)

 

(d)

(e)

 

(f)

 (g)

 

(h)

(i)

Fig. 2. Experimental results; (a) output voltage; (b) output voltage and current; (c) generated voltage levels by right side; (d) generated voltage levels by left side; (e) generated voltage levels by L,1 u ; (f) voltage across R2,2 S ; (g)

voltage across 1 T ; (h) voltage across 3 T ; (i) voltage across a T .

 

CONCLUSION:

In this paper, a new combined cascaded multilevel inverter has been proposed. After that, five different algorithms are proposed in order to determine the magnitudes of the DC voltage sources. By comparing these algorithms, it was concluded that the algorithm which generates a high number of voltage levels with less number of switches and DC voltage sources is better than other algorithms. According to this comparison, it was found that the fifth proposed algorithm is better among the proposed algorithms. In order to prove the claim about reduction of the number of IGBTs and DC voltage sources in the proposed topology, this topology was compared to presented topologies from different aspects. In these comparisons, it was found that the proposed topology generates 31 voltage levels with 14 IGBTs while presented topologies in [4], [10] and [12] generate the same number of voltage levels with 32, 16 and 34 IGBTs, respectively. Also, it was found that this number of voltage levels needs 4 DC voltage sources, whereas, the topologies which presented in [4] and [12] generate 17 and 9 voltage levels with the same  number of DC voltage sources. Afterwards, correctness of performance of the proposed topology and relations have been verified through experimentation of the proposed topology with 2 input units in each side.

REFERENCES:

[1] C.I. Odeh, E.S. Obe, and O. Ojo,: “Topology for cascaded multilevel inverter,” IET Power Electron., vol. 9, no. 5, pp. 921-929, April 2016.

[2] E. Zamiri, N. Vosoughi, S.H. Hosseini, R. Barzegarkhoo, and M. Sabahi, “A new cascaded switched-capacitor multilevel inverter based on improved series–parallel conversion with less number of components,” IEEE Trans. Ind. Electron., vol. 63, no. 6, pp. 3582-3594, June 2016.

[3] N. Prabaharan and K. Palanisamy, “Analysis of cascaded H-bridge multilevel inverter configuration with double level circuit,” IET Power Electron., vol. 10, no. 9, pp. 1023-1033, July 2017.

[4] M.R. Banaei, M.R. Jannati Oskuee and H. Khounjahan, “Reconfiguration of semi-cascaded multilevel inverter to improve systems performance parameters,” IET Power Electron., vol. 7, no. 5, pp. 1106-1112, May 2014.

[5] E. Babaei, S. Laali, and Z. Bayat, “A single-phase cascaded multilevel inverter based on a new basic unit with reduced number of power switches,” IEEE Trans. Ind. Electron., vol. 62, no. 2, pp. 922-929, Feb. 2015.