Z-network Plus Switched-capacitor Boost DC-DC Converters

 ABSTRACT:

In this paper, two Z-network plus switched-capacitor based DC-DC boost converters (ZSCBC) are proposed. The integration of the Z-network with switched-capacitor is responsible for yielding a high voltage gain and that too at lower duty ratios compared to the conventional quasi Z-source DC-DC converter (QZSC). Since the proposed converters contains Z or impedance-network, the operating duty ratio is less than 0.5 like in QZSC and retains its advantages such as common ground and low voltage stress on Z-network capacitors. Unlike QZSC, the switch and all the diode voltage stresses in the proposed converters is low even at high voltage gains. A detailed steadystate analysis is presented to identify the salient features of the proposed Z- network based boost converter and thereafter compared with other Z-source based configurations. Small-signal analysis is established and a single-loop voltage mode controller is designed. A 48 to 250 V, 130 W prototype is built to demonstrate the effectiveness of the ZSCBC. The steady-state and closed-loop response measurements validate the theoretical studies.

KEYWORDS:

1.      Boost converter

2.      Switched-capacitor

3.      Quasi-Z source DC-DC Converter

4.       Z-source Inverter

SOFTWARE: MATLAB/SIMULINK

 CONCLUSION:

Two Z-network plus switched capacitor based DC-DC boost converters (ZSCBC) were proposed in this paper exhibiting voltage gain higher than QZSC while keeping the main advantages of QZSC intact such as low Z-network capacitor voltage stress, common ground and wider duty ratio range. The steady-state analysis of the ZSCBC and its comparison with other reported Topologies-1 to 7revealed that (i) the voltage stress of the switch and all the diodes is equal irrespective of their physical location, (ii) lower switch and diodes stress even at high voltage gain, and (iii) voltage gain enhancement through addition of a diode-capacitor network. Unlike the proposed converter, the Topologies-1 to 6 unable to incorporate the voltage gain enhancement feature. Detailed analysis was established and a single-loop voltage-mode controller was designed to ensure closed-loop stabilization of ZSCBC. Experimental measurements demonstrated the effectiveness of PID-type controller in terms of regulation against sudden changes in the load and source voltage. Furthermore, the controller designed was equally effective in rejecting low frequency disturbances present in the source.

 

REFERENCES:

[1] M. Forouzesh, Y. P. Siwakoti, S. A. Gorji, F. Blaabjerg and B. Lehman, "Step-Up DC–DC converters: A comprehensive review of voltageboosting techniques, topologies, and applications," in IEEE Trans. On Power Electron., vol. 32, no. 12, pp. 9143-9178, Dec. 2017.

[2] X. G. Feng, J. J. Liu and F. C. Lee: ‘Impedance specifications for stable dc distributed power systems’, in IEEE Trans. Power Electron., vol. 17, no. 2, pp. 157–162, Mar. 2002.

[3] F. Z. Peng, "Z-source inverter," in IEEE Trans. Ind. Appl., vol. 39, no. 2, pp. 504-510, Mar/Apr. 2003.

[4] J. Anderson and F. Z. Peng, "Four quasi-Z-Source inverters," in Proc. IEEE PESC, pp. 2743-2749, 2008.

[5] Y. P. Siwakoti, F. Z. Peng, F. Blaabjerg, P. C. Loh, and G. E. Town, “Impedance-source networks for electric power conversion part-I: A topological review”, in IEEE Trans. on Power Electron., vol. 30, no. 2,pp.699-716, Feb. 2015.

Symmetrical and Asymmetrical Reduced Device Multilevel Inverter Topology

 ABSTRACT:

This paper presents a single-phase symmetrical and asymmetrical multilevel inverter (MLI) topology. The presented topology can generate 9-level output voltage in a symmetrical configuration, 13-level and 17-level in asymmetrical configuration with a single cell. The number of output levels can be improved further by increasing either the number of cells or switches in a single cell. The presented topology contains the least number of DC sources, semiconductor switches, capacitors and diodes as compared to classical and recently proposed topologies. Reduction in component count decreases the size, complexity and cost of the overall converter. A detailed comparison has been done of the presented topology with recently proposed topologies in terms of DC sources, semiconductor switches, capacitor and total blocking voltage. Finally, to validate the presented concept, the prototype of the presented nine-level. Thirteen-level and seventeen-level MLI topologies have been tested in the laboratory for different switching frequencies, different modulation indexes, sudden load changes and nonlinear load.

KEYWORDS:

1.      Multilevel inverter topology

2.      Phase opposing disposition pulse width modulation

3.      Reduced device count

4.      Symmetrical and asymmetrical topology

5.      Total blocking voltage

SOFTWARE: MATLAB/SIMULINK

 CONCLUSION:

This paper presented a symmetrical and asymmetrical MLI topology that can be used in high power/ high voltage applications with equal and unequal DC voltage sources. The presented topology generates nine-level output voltage in a symmetrical configuration, thirteen-level output voltage in asymmetrical binary (1:2) configuration and seventeen-level output voltage in asymmetrical trinary (1:3) configuration. The topology comprises the least number of power semiconductor switches, isolated DC sources, capacitors, diodes and low total blocking voltage on the switches as compared to classical and recently presented topologies. A detailed comparison of the presented topology with recently proposed topologies proves the superiority in aspects of component count and total blocking voltage which decreases the cost and increases the efficiency of the system. The performance of the presented topology has been tested through simulation and experimental validation shows the electrical feasibility of 9-/13-/17 level inverter.

REFERENCES:

[1] Morrison, J.,''Global Demand Projections for Renewable Energy Resources'', IEEE Canada Electrical Power Conference, Montreal, Que., pp. 537-542, Oct. 2007.

[2] Benner, J. P., Kazmerski, L.,''Photovoltaics gaining greater visibility'', IEEE spectrum, vol.36, no.9, pp. 34-42, Sep.1999.

[3] Zhao, Y.; Xiang, X.; Li, C.; Gu, Y.; Li, W.; He, X.,''Single-Phase High Step-up Converter with Improved Multiplier Cell Suitable for Half- Bridge-Based PV Inverter System'', in IEEE Transactions on Power Electronics, vol.29, no.6, pp. 2807-2816, Jul.2013.

[4] Y, Liao.; and C, Lai.,''Newly-Constructed Simplified Single-Phase Multistring Multilevel Inverter Topology for Distributed Energy Resources'', in IEEE Transactions on Power Electronics, vol.26, no.9, pp. 2386-2392, May. 2011.

[5] Rodríguez, J.; Bernet, S.; Wu, B.; Pontt, J. O.; Kouro, S., ''Multilevel voltage-source-converter topologies for industrial medium-voltage drives''. IEEE Transactions on industrial electronics, vol. 54, no.6, pp.2930-2945, Oct.2007.

A New Multilevel Inverter Topology With Reduce Switch Count

 ABSTRACT:

Multilevel inverters are a new family of converters for dc_ac conversion for the medium and high voltage and power applications. In this paper, two new topologies for the staircase output voltage generations have been proposed with a lesser number of switch requirement. The first topology requires three dc voltage sources and ten switches to synthesize 15 levels across the load. The extension of the first topology has been proposed as the second topology, which consists of four dc voltage sources and 12 switches to achieve 25 levels at the output. Both topologies, apart from having lesser switch count, exhibit the merits in terms of reduced voltage stresses across the switches. In addition, a detailed comparative study of both topologies has been presented in this paper to demonstrate the features of the proposed topologies. Several experimental results have been included in this paper to validate the performances of the proposed topologies with different loading condition and dynamic changes in load and modulation indexes.

KEYWORDS:

1.      Asymmetric, hybrid inverter

2.      Inverter topology

3.      Multilevel inverter

4.      MLI

5.      Nearest level control

6.      Power electronics

7.      Single-phase inverter

8.      Reduce switch count

SOFTWARE: MATLAB/SIMULINK

CONCLUSION:

This paper presents a new assembly of multilevel inverter topology with consideration of reduced switch count. The proposed topology has been discussed in details with the basic unit with 3S-15L configuration generating 15 levels, and the extension of the proposed topology with 4S-25L configuration to achieves 25 levels. Two generalized structure of the proposed topology has also been proposed. A detailed comparative study has been carried out with the proposed topology and recently reported topologies with three and four dc voltage sources. Finally, several experimental results proves the suitability and workability of the proposed topology with different type of loading combinations considering the change of modulation indexes.

REFERENCES:

[1] H. Akagi, ``Multilevel converters: Fundamental circuits and systems,'' Proc. IEEE, vol. 105, no. 11, pp. 2048_2065, Nov. 2017.

[2] J. I. Leon, S. Vazquez, and L. G. Franquelo, ``Multilevel converters: Control and modulation techniques for their operation and industrial applications,'' Proc. IEEE, vol. 105, no. 11, pp. 2066_2081, Nov. 2017.

[3] J. Rodríguez, J.-S. Lai, and F. Z. Peng, ``Multilevel inverters: A survey of topologies, controls, and applications,'' IEEE Trans. Ind. Electron., vol. 49, no. 4, pp. 724_738, Aug. 2002.

[4] S. Kouro et al., ``Recent advances and industrial applications of multilevel converters,'' IEEE Trans. Ind. Electron., vol. 57, no. 8, pp. 2553_2580, Aug. 2010.

[5] N. Prabaharan and K. Palanisamy, ``A comprehensive review on reduced switch multilevel inverter topologies, modulation techniques and applications,'' Renew. Sustain. Energy Rev., vol. 76, pp. 1248_1282, Sep. 2017.

 

Control of Solar Photovoltaic Integrated UniversalActive Filter Based on Discrete Adaptive Filter

ABSTRACT:

In this work, a novel technique based on adaptive filtering is proposed for the control of three phase universal active power filter with a solar photovoltaic array integrated at its DC bus. Two adaptive filters along with a zero crossing detection technique, are used to extract the magnitude of fundamental active component of distorted load currents, which is then used in estimation of reference signal for the shunt active filter. This technique enables extraction of active component of all three phases with reduced mathematical computation. The series active filter control is based on synchronous reference frame theory and it regulates load voltage and maintains it in-phase with voltage at point of common coupling under conditions of voltage sag and swell. The performance of the system is evaluated on an experimental prototype in the laboratory under various dynamic conditions such as sag and swell in voltage at point of common coupling, load unbalancing and change in solar irradiation intensity.

KEYWORDS:

1.      Power quality

2.      Universal active power filter

3.      Adaptive filtering

4.      Photovoltaic system

5.      Maximum power point tracking

6.      Quadrature signal generation

SOFTWARE: MATLAB/SIMULINK

 CONCLUSION:

The performance of adaptive filter based PV-UAPF system under both steady state and dynamic conditions, have been analyzed in detail. The method of sampling the fundamental component of load current obtained through adaptive filter enables fast extraction of fundamental active component of nonlinear load currents for all phases in one sampling. Only two adaptive filters are required to extract magnitude of active component of three phase load currents. This technique requires reduced computational resources while achieving good dynamic and steady state performance in extraction of fundamental active component of nonlinear load current. The system performance has been found to be satisfactory under various disturbances in load current, PCC voltage and solar irradiation. The series active filter is able to regulate load voltage at 220 V under variations of PCC voltage from 170 V to 270 V. The grid current THD is maintained at approximately 3% even though the THD of load current is 28% thus meeting requirement of IEEE-519 standard. The PV-UAPF system has been able to maintain the grid currents balanced under unbalanced loading condition.

The proposed topology and algorithm are suited for employing in conditions where PCC voltage sags/swells and load current harmonics are major power quality issues. Certain power quality issues not addressed include voltage distortions, flicker, neutral current compensation etc. This power quality issues can be addressed by modification of topology and control algorithm according to the requirements in the distribution system. The PV-UAPF system provides dual benefit of distributed generation as well as improving power quality of the distribution system.

REFERENCES:

 [1] N. R. Tummuru,M. K. Mishra, and S. Srinivas, “Dynamic energy management of hybrid energy storage system with high-gain pv converter,” IEEE Transactions on Energy Conversion, vol. 30, no. 1, pp. 150–160, March 2015.

[2] B. Singh, A. Chandra, K. A. Haddad, Power Quality: Problems and Mitigation Techniques. London: Wiley, 2015.

[3] S. Devassy and B. Singh, “Control of solar photovoltaic integrated upqc operating in polluted utility conditions,” IET Power Electronics, vol. 10, no. 12, pp. 1413–1421, Oct 2017.

[4] S. Devassy and B. Singh, “Performance analysis of proportional resonant and adaline-based solar photovoltaic-integrated unified active power filter,” IET Renewable Power Generation, vol. 11, no. 11, pp. 1382– 1391, 2017.

[5] L. Ramya and J. Pratheebha, “A novel control technique of solar farm inverter as pv-upfc for the enhancement of transient stability in power grid,” in 2016 International Conference on Emerging Trends in Engineering, Technology and Science (ICETETS), Feb 2016, pp. 1–7.                                         

A New Circuit of Modular Multilevel Inverter for Grid-Connected Photovoltaic Conversion Plants

ABSTRACT:

This study presents a new circuit topology of the Modular Multilevel Converter (MMC) which is deployed for photovoltaic grid applications. In the conventional MMC, two arm inductors are placed in each phase to limit the circulating current. In the proposed topology, the inductors are replaced by a transformer. The proposed circuit gives a 50% reduction of the voltage rating of the power devices and the capacitors in comparison with the conventional MMC. The required dc-link voltage which is fed directly by PV panels is also reduced by half. The paper presents a PWM method to control the solar inverter output voltage. The proposed concept is confirmed through simulation and experimental results.

KEYWORDS:

1.      Photovoltaic (PV) conversion

2.      Modular multilevel converter

3.      Pulse width modulation

4.      Parameter

SOFTWARE: MATLAB/SIMULINK

CONCLUSION:

In this paper, the feasibility of a new circuit topology for the MMC has been outlined, where it is deployed as an interface between the grid and PV modules. With this arrangement, the voltage rating of capacitors and the power semiconductor devices are effectively reduced by half. The dc bus magnitude which is formed by the dc output from PV array is also reduced by half. A method to suppress the 2nd harmonic current in the inverter has been discussed. The concept of level-shifted PWM, where the modulating waveform is shifted and scaled to bring inside one carrier, has been used to reduce the switching frequency. With this, there is no need to calculate the duty cycle of individual cells. The proposed idea has been verified by simulation and experimental results under disturbance in the system caused by solar irradiance changes.

REFERENCES:

[1] Q.-C. Zhong and T. Hornik, Control of Power Inverters in Renewable Energy and Smart Grid Integration, Hoboken, NJ: Wiley, 2013.

[2] A. G. Golnas, “PV system reliability: An operator’s perspective,” IEEE J. Photovolt., Vol. 3, No. 1, pp. 416-421, Jan. 2013.

[3] International Energy Agency. (2010, May). Technology Roadmap, Solar Photovoltaic Energy [Online].

[4] E. Romero-Cadaval, G. Spagnuolo, L. G. Franquelo, et al., “Grid-Connected Photovoltaic Generation Plants,” IEEE Ind. Electron. Mag., Vol. 7, No. 3, pp. 6-20, Sept. 2013.

[5] M. G. Villalva, J. R. Gazoli and E. R. Filho, “Comprehensive Approach to Modeling and Simulation of Photovoltaic Arrays,” IEEE Trans. Power Electron, Vol. 24, No. 5, pp. 1198-1208, May 2009.

Selective Harmonics Elimination Technique in Single Phase Unipolar H-Bridge Inverter

ABSTRACT:  

Specific odd harmonics can be mitigated by operating the semiconductor switches in H-bridge inverters at optimized switching angles of the PWM signals. These switching angles can be achieved by deriving a number of nonlinear equations using Selective Harmonic Elimination Pulse Width Modulation (SHEPWM) method. Modulation index (m) is a significant parameter used to control the amplitude of the fundamental output voltage of DC-AC inverter. By changing the value of modulation index the Total Harmonics Distortion (THD) also will change. In this paper, the performance of single phase full-bridge inverter using SHE-PWM scheme with varying the modulation index is evaluated. In order to achieve a minimum THD, a different number of nonlinear equations are used to calculate the switching angles. The performance of a single phase unipolar inverter is simulated in Matlab.

KEYWORDS:

1.      Selective Harmonic Elimination

2.      H-bridge Inverter

SOFTWARE: MATLAB/SIMULINK

CONCLUSION:

Matlab-Simulink is used to evaluate the proposed technique in order to mitigate 3th, 5th, 7th, 9th, 11th & 13^th harmonics and to verify the influence of various condition of modulation index on THD in single-phase full-bridge H inverter. Low order odd harmonics can be mitigated successfully by using SHE-PWM also, by adjusting the switching angles the Total Harmonic Distortion is decreased to a minimum of 57.47%. These switching angles are applied to generate control signals of full-bridge H-inverter. By increasing the modulation index the THD decreased. Also, the fundamental voltage of the inverter is maximized by variation of modulation index with switching angles optimized.

REFERENCES:

[1]. Ashok, B., & Rajendran, A. (2013). Selective Harmonic Elimination of Multilevel Inverter Using SHEPWM Technique. International Journal of Soft Computing and Engineering (IJSCE), 3(2), 79–82.

[2]. Basri, A. B., Zaidi, N. A., Bopi, N. B., Aboadla, E. H., Khan, S., & Habaebi, M. H. (2016). EFFECTS OF SWITCHING FREQUENCY TO SERIES LOADED SERIES RESONANT CIRCUIT. ARPN Journal of Engineering and Applied Sciences, 11(1), 382–386.

[3]. Dahidah, M. S. A., & Agelidis, V. G. (2007). Non-symmetrical selective harmonic elimination PWM techniques: The unipolar waveform. PESC Record - IEEE Annual Power Electronics Specialists Conference, 1885–1891.

[4]. Edpuganti, K. (2015). Fundamental Switching Frequency Optimal Pulse width Modulation of Medium-Voltage Nine-Level Inverter. IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, 62(7), 4096– 4104.

[5]. Ghalib, M. A., & Abdalla, Y. S. (2014). Design and Implementation of a Pure Sine Wave Single Phase Inverter for Photovoltaic Applications. AMERRICAN SOCIETY FOR ENGINEERING EDUCATION, ASEE, 1– 8.

Selective Harmonic Elimination (SHE) for 3-Phase Voltage Source Inverter (VSI)

 ABSTRACT:

 The Selective Harmonic Elimination (SHE) for 3-Phase Voltage Source Inverter (VSI) is presented here. The projected work investigates the Selective Harmonic Elimination (SHE) to eliminate harmonics produced by Pulse Width Modulation (PWM) inverter. The selective harmonic elimination method for three phase Voltage Source Inverter (VSI) is generally based on ideas of opposite harmonic injection. In this proposed scheme, the lower order harmonics (3rd, 5th, 7th, and 9th) are eliminated by the dominant harmonics of same order generated in opposite phase by Sinusoidal Pulse Width Modulation (SPWM) inverter and by using this scheme the Total Harmonic Distortion (THD) is reduced. Analysis of Sinusoidal Pulse Width Modulation (SPWM) technique and Selective Harmonic Elimination (SHE) is simulated using MATLAB/SIMULINK model.

KEYWORDS:

1.      Selective Harmonic Elimination (SHE)

2.      Pulse Width Modulation (PWM) e

3.      Total Harmonic Distortion (THD) and Voltage Source Inverter (VSI)

 SOFTWARE: MATLAB/SIMULINK

 CONCLUSION:

The paper presents a selective harmonic elimination technique for three phase voltage source inverter with the RL load. A Three phase Voltage Source Inverter (VSI) changes DC input voltage to a three phase variable frequency variable voltage output. The elimination of specific low-order harmonics from a given voltage/current waveform achieved by Selective Harmonic Elimination (SHE) technique. We unite the inductor filter with the capacitor the ripple aspect will turn out to be more or less autonomous of the load filter. Finally Analysis and comparison of Total Harmonic Distortion (THD) for sinusoidal Pulse Width Modulation (PWM) technique and selective harmonic elimination technique has been done. From the comparison it is very apparent that the Total Harmonic Distortion (THD) for selective harmonic technique is less than that of sinusoidal Pulse Width Modulation (PWM) method.

REFERENCES:

[1] Ray, R.N., Chatterjee, and Goswami, S.K, “Reduction of voltage harmonic using optimization – based combined approach on” proceeding on IET Power Electronics, 3 (3). 334-344. 2008.

[2] Mohamed S.A.Dahidah and Vassilios G. Agelidis, “Selective harmonic elimination PWM control for Cascaded multilevel voltage source converters: A generalized formula” IEEE Trans on power electronics, 23(4). 1620-1630. Jul. 2008.

[3] Wells, Jason R. Xin Geng, Chapman, Patrick L. and Krein, Philip T. “Modulation based harmonic elimination” IEEE Transactions on Power Electronics, 22(1). 2007.

[4] Fellow, Javier Napoles, Jose Ignacio Leon, and Aguirre, Miguel A. “A flexible selective harmonic mitigation to meet grid codes in three level PWM converters” IEEE Transactions on Industrial Electronics, 54(6).Dec.2007.

[5] Hadji, S. Touhami O. and C.J.Goodman, “Vector- optimized harmonic elimination for single- phase pulse width modulation inverters/converters” IET Electr.Power Appl.,1(3). 423-432. 2007