Symmetrical and Asymmetrical Reduced Device Multilevel Inverter Topology

 ABSTRACT:

This paper presents a single-phase symmetrical and asymmetrical multilevel inverter (MLI) topology. The presented topology can generate 9-level output voltage in a symmetrical configuration, 13-level and 17-level in asymmetrical configuration with a single cell. The number of output levels can be improved further by increasing either the number of cells or switches in a single cell. The presented topology contains the least number of DC sources, semiconductor switches, capacitors and diodes as compared to classical and recently proposed topologies. Reduction in component count decreases the size, complexity and cost of the overall converter. A detailed comparison has been done of the presented topology with recently proposed topologies in terms of DC sources, semiconductor switches, capacitor and total blocking voltage. Finally, to validate the presented concept, the prototype of the presented nine-level. Thirteen-level and seventeen-level MLI topologies have been tested in the laboratory for different switching frequencies, different modulation indexes, sudden load changes and nonlinear load.

KEYWORDS:

1.      Multilevel inverter topology

2.      Phase opposing disposition pulse width modulation

3.      Reduced device count

4.      Symmetrical and asymmetrical topology

5.      Total blocking voltage

SOFTWARE: MATLAB/SIMULINK

 CONCLUSION:

This paper presented a symmetrical and asymmetrical MLI topology that can be used in high power/ high voltage applications with equal and unequal DC voltage sources. The presented topology generates nine-level output voltage in a symmetrical configuration, thirteen-level output voltage in asymmetrical binary (1:2) configuration and seventeen-level output voltage in asymmetrical trinary (1:3) configuration. The topology comprises the least number of power semiconductor switches, isolated DC sources, capacitors, diodes and low total blocking voltage on the switches as compared to classical and recently presented topologies. A detailed comparison of the presented topology with recently proposed topologies proves the superiority in aspects of component count and total blocking voltage which decreases the cost and increases the efficiency of the system. The performance of the presented topology has been tested through simulation and experimental validation shows the electrical feasibility of 9-/13-/17 level inverter.

REFERENCES:

[1] Morrison, J.,''Global Demand Projections for Renewable Energy Resources'', IEEE Canada Electrical Power Conference, Montreal, Que., pp. 537-542, Oct. 2007.

[2] Benner, J. P., Kazmerski, L.,''Photovoltaics gaining greater visibility'', IEEE spectrum, vol.36, no.9, pp. 34-42, Sep.1999.

[3] Zhao, Y.; Xiang, X.; Li, C.; Gu, Y.; Li, W.; He, X.,''Single-Phase High Step-up Converter with Improved Multiplier Cell Suitable for Half- Bridge-Based PV Inverter System'', in IEEE Transactions on Power Electronics, vol.29, no.6, pp. 2807-2816, Jul.2013.

[4] Y, Liao.; and C, Lai.,''Newly-Constructed Simplified Single-Phase Multistring Multilevel Inverter Topology for Distributed Energy Resources'', in IEEE Transactions on Power Electronics, vol.26, no.9, pp. 2386-2392, May. 2011.

[5] Rodríguez, J.; Bernet, S.; Wu, B.; Pontt, J. O.; Kouro, S., ''Multilevel voltage-source-converter topologies for industrial medium-voltage drives''. IEEE Transactions on industrial electronics, vol. 54, no.6, pp.2930-2945, Oct.2007.