Multilevel Inverter Topologies with ReducedDevice Count: A Review

 

ABSTRACT:

 Multilevel inverters have created a new wave of interest in industry and research. While the classical topologies have proved to be a viable alternative in a wide range of highpower medium-voltage applications, there has been an active interest in the evolution of newer topologies. Reduction in overall part count as compared to the classical topologies has been an important objective in the recently introduced topologies. In this paper, some of the recently proposed multilevel inverter topologies with reduced power switch count are reviewed and analysed. The paper will serve as an introduction and an update to these topologies, both in terms of the qualitative and quantitative parameters. Also, it takes into account the challenges which arise when an attempt is made to reduce the device count. Based on a detailed comparison of these topologies as presented in this paper, appropriate multilevel solution can be arrived at for a given application.

KEYWORDS:

1.      Multilevel inverters

2.      Reduced device count

3.      Even power distribution

4.       Fundamental switching frequency operation

5.      Source configuration

SOFTWARE: MATLAB/SIMULINK

CONCLUSION:  

As multilevel inverters continue to gain increasing importance for both high power and low power applications, many researchers have proposed specific topological solutions for intended applications. Also, newer multilevel topologies have been proposed, offering high output resolution with a reduced number of power switches. In this paper, a review of nine reduced device count multilevel topologies is presented. Based on the review, it can be concluded that in the process of reducing the power switch count, various compromises are involved such as:

i. Increased voltage rating of semiconductor switches.

ii. Requirement of bidirectional switches

iii. Increased number of sources and/or requirement of asymmetric input DC levels.

iv. Loss of modularity.

v. Reduced number of redundant states.

vi. Complex modulation / control schemes.

vii. Difficulty in possibility of charge balance control.

In this paper, qualitative and quantitative features of RDC-MLI topologies have been discussed and a comparison has been made so as to facilitate a well-informed selection of topology for a given application. In addition, the paradigm presented in the paper will also help to evaluate the RDC-MLI topologies that will be proposed in future.

REFERENCES:

[1] Espinoza, J. R.;, "Inverters," Power Electronics Handbook, MH Rashid (Ed.), pp. 225-269, 2001.

[2] Abbott, D.;, "Keeping the Energy Debate Clean: How Do We Supply the World's Energy Needs?," Proceedings of the IEEE , vol.98, no.1, pp.42-66, Jan. 2010.

[3] Xinghuo, Y.; Cecati, C.; Dillon, T.; SimoÞes, M.G.;, "The New Frontier of Smart Grids," Industrial Electronics Magazine, IEEE , vol.5, no.3, pp.49-63, Sept. 2011.

[4] Daher, S.;,“ Analysis, design and implementation of a high efficiency multilevel converter for renewable energy systems” , PhD Dissertation Submitted to Kassel University, Kassel, Germany, 2006, Available: http://www.uni-kassel.de/upress/online/frei/978-3-89958-236-9.volltext.frei.pdf.

[5] Franquelo, L.G.; Rodriguez, J.; Leon, J.I.; Kouro, S.; Portillo, R.; Prats, M.A.M.; , "The age of multilevel converters arrives," Industrial Electronics Magazine, IEEE , vol.2, no.2, pp.28-39, June 2008.

Modified Seven-Level Pack U-Cell Inverter forPhotovoltaic Applications

 ABSTRACT:

 This paper proposes a modified configuration of single-phase Pack U-Cell (PUC) multilevel inverter in which the output voltage has higher amplitude than the maximum DC link value used in the topology as a boost operation. The introduced inverter generates seven-level AC voltage at the output using two DC links and six semiconductor switches. Comparing to cascaded H-bridge and neutral point clamp multilevel inverters, the introduced multilevel inverter produces more voltage levels using less components. The proposed inverter is used in PV system where the green power comes from two separate PV panels connected to the DC links through DC-DC converters to draw the maximum power. Due to boost operation of this inverter, two different PV panels can combine and send their powers to the grid. Simulations and experimental tests are conducted to investigate the good dynamic performance of the inverter in grid-connected PV system.

 KEYWORDS:

1.      PV Inverter

2.      Pack U-Cell

3.      Modified Pack U-Cell

4.      PUC5

5.       MPUC5

6.      Power Quality

7.       Renewable Energy Conversion

SOFTWARE: MATLAB/SIMULINK

CONCLUSION:  

In this paper a modified multilevel inverter topology has been presented. The proposed MPUC inverter can generate 7-level voltage waveform at the output with low harmonic contents. Unlike the reported PUC topology, the 7-level MPUC inverter is capable to produce voltage levels more than the DC sources used in the structure. It can sum up the DC buses amplitudes to deliver more power to the output. The associated switching algorithm has been designed and implemented on the introduced MPUC topology with reduced switching frequency aspect. Moreover, photovoltaic application has been targeted for this inverter to deliver power from PV panels with different voltage/current rating to grid. In this regard, results have been shown to validate the acceptable voltage regulation and current controlling of the grid-connected inverter as well as the implemented P&O MPPT algorithm.

REFERENCES:

[1] B. Singh, A. Chandra, and K. Al-Haddad, Power Quality: Problems and Mitigation Techniques: John Wiley & Sons, 2014.

[2] I. Gowaid, G. Adam, A. Massoud, S. Ahmed, and B. Williams, "Hybrid and Modular Multilevel Converter Designs for Isolated HVDC-DC Converters," IEEE Journal Emerg. and Select. Topics in Power Electron., vol. PP, no. 99, p. 1, 2017.

[3] H. Vahedi, K. Al-Haddad, Y. Ounejjar, and K. Addoweesh, "Crossover Switches Cell (CSC): A New Multilevel Inverter Topology with Maximum Voltage Levels and Minimum DC Sources," in IECON 2013-39th Annual Conference on IEEE Industrial Electronics Society, Austria, 2013, pp. 54-59.

[4] P. W. Hammond, "A new approach to enhance power quality for medium voltage drives," in Petroleum and Chemical Industry Conference, 1995. Record of Conference Papers., Industry Applications Society 42nd Annual, 1995, pp. 231-235.

[5] A. Nabae, I. Takahashi, and H. Akagi, "A new neutral-point-clamped PWM inverter," IEEE Trans. Ind. Applications, no. 5, pp. 518-523, 1981.

Packed E-Cell (PEC) Converter TopologyOperation and Experimental Validation

ABSTRACT:

 

This paper proposes a novel single-dc-source multilevel inverter called Packed E-Cell (PEC) topology to achieve nine levels with noticeably reduced components count, while dc capacitors are actively balanced. The nine-level PEC (PEC9) is composed of seven active switches and two dc capacitors that are shunted by a four-quadrant switch to from the E-cell, and it makes use of a single dc link. With the proper design of the corresponding PEC9 switching states, the dc capacitors are balanced using the redundant charging/discharging states. Since the shunted capacitors are horizontally extended, both capacitors are simultaneously charged or discharged with the redundant states, so only the auxiliary dc-link voltage needs to be sensed and regulated to half of the input dc source voltage, and consequently, dc capacitors' voltages are inherently balanced to one quarter of the dc bus voltage. To this end, an active capacitor voltage balancing integrated to the level-shifted half-parabola carrier PWM technique has been designed based on the redundant charging/discharging states to regulate the dc capacitors voltages of PEC9. Furthermore, using the E-cell not only reduces components count but also the proposed topology permits multi ac terminal operation. Thus, Five-level inverter operation can be achieved during the four-quadrant switch fault, which confers to the structure high reliability. The theoretical analysis as well as the experimental results are presented and discussed, showing the basic operation, multi-functionality, as well as the superior performance of the proposed novel PEC9 inverter topology.

 KEYWORDS:

 

1.      Nine-level Packed E-Cell (PEC)

2.      Single-dc source inverter

3.      Single auxiliary dc-link capacitors

4.       Multilevel converter

5.      PUC converter

6.       Active rectifier

7.      Active filter

8.      Grid-connected converter

SOFTWARE: MATLAB/SIMULINK

CONCLUSION:

In this paper, a novel nine-level single-DC source Packed E-Cell (PEC9) topology has been introduced as a promising candidate for single-phase inverter suitable for symmetrical and asymmetrical series of connection. The presented structure is indeed an optimized compact design topology which permits the reduction of auxiliary DC-link and components count by using E-Cell type of connection. Moreover, by horizontal extension of auxiliary DC-link, in the form of E-Cells, simultaneous charging or discharging with redundant state are achieved that guarantees floating capacitors voltage balancing under all operating conditions. An active voltage balancing algorithm was integrated to the half parabola carrier PWM based technique to efficiently regulate floating capacitors voltages. It was also demonstrated that different output stepped voltage waveforms are achievable without changing in converter circuit design. The presented experimental results of PEC9 validated its reliable performance in keeping capacitors voltages balanced under different load and source conditions that can emerge as a competitive topology for various industrial standalone and grid-tied applications.

REFERENCES:

[1] M. Norambuena, S. Kouro, S. Dieckerhoff, and J. Rodriguez, ``Reduced multilevel converter: A novel multilevel converter with a reduced number of active switches,'' IEEE Trans. Ind. Electron., vol. 65, no. 5, pp. 3636_3645, May 2018.

[2] H. Vahedi, A. A. Shojaei, L.-A. Dessaint, and K. Al-Haddad, ``Reduced DC-link voltage active power _lter using modi_ed PUC5 converter,'' IEEE Trans. Power Electron., vol. 33, no. 2, pp. 943_947, Feb. 2018.

[3] H. Aburub, J. Holtz, and J. Rodriguez, ``Medium-voltage multilevel converters-state of the art, challenges, and requirements in industrial applications,'' IEEE Trans. Ind. Electron, vol. 57, no. 8, pp. 2581_2596, Dec. 2010.

[4] N. Arun and M. M. Noel, ``Crisscross switched multilevel inverter using cascaded semi-half-bridge cells,'' IET Power Electron., vol. 11, no. 1, pp. 23_32, Jan. 2017.

[5] E. Babaei and S. Laali, ``Optimum structures of proposed new cascaded multilevel inverter with reduced number of components,'' IEEE Trans. Ind. Electron., vol. 62, no. 11, pp. 6887_6895, Nov. 2015.

Modified Multilevel Inverters with Reduced Structures Based on Packed U-Cell

 ABSTRACT:

 Multilevel inverters are capable of generating high-quality staircase pseudo-sinusoidal voltage waveform with low THD. These types of topologies may require large number of switches and power supplies. This leads to higher cost and volume of the converter along with complicated control algorithms. Recently, a branch of multilevel converters is emerged as compact power conversion units, in which their ‘reduced-structure’ topologies use lower number of active and passive devices compared with the available topologies. Packed U-Cell, a new reduced-structure multilevel converter, has been recently reported in the literature to reduce component count. Packed U-Cell requires lesser active switches as compared to the existing counterparts. However, there are some drawbacks associated with this topology such as restricted maximum output voltage, high voltage stress on switches, and limited performance to low voltage applications. Available literature present generalization of the topology with special asymmetrical source-ratio, but no sufficient and effective investigations have been made for modified structures or other symmetrical or asymmetrical source-ratio with cascaded configurations. In this paper, the issues associated with PUC are addressed and two approaches as remedy are presented. The first approach presents a comprehensive analysis of cascaded topologies with the proposed basic units, and the second approach is related to a new modified configuration on the basis of the conventional converter for improving the performance of the PUC in terms of total blocking voltage, switch ratings and extending its performance to high voltage applications. Moreover, design of a novel 49-level modified structure and 147-level cascade inverter based on conventional PUC are analyzed under optimal number of DC sources and power switches to get the best possible topology as a solution. Finally, experimental validations were performed by implementing laboratory prototypes.

KEYWORDS:

 

1.      Asymmetrical DC Sources

2.      Multilevel inverter

3.      Modified structure

4.      Packed U-Cell

5.      Reduced structures

SOFTWARE: MATLAB/SIMULINK

CONCLUSION:   

In this paper different drawbacks associated with a newly introduced multilevel converter, named as Packed U-Cell (PUC), such as restricted maximum output voltage, high voltage stress on switches, and limited performance to low voltage applications, are presented. For solving these drawbacks, no sufficient investigations in literature have been made as modified structures or other symmetrical or asymmetrical cascaded configurations. The motivation for conducting this study is to achieve more voltage levels with reduction in the number of power electronics components with lower ratings and blocking voltages, and extending its performance to high voltage applications, using cascaded (approach 1) or modified (approach 2) structures. In the first approach, analysis showed that with using only two DC sources in each cascaded module (..=2), the CAPUC1 and CAPUC2 generate the maximum number of voltage levels with a fixed number of DC sources and switches. Using more than two DC sources in each module, the CAPUC1 generates more voltage levels. Consequently, the CAPUC1 has the optimal structure among all discussed cascade structures. In the second one, the proposed modified structure can improve conventional PUC performance based on power switch ratings for high power applications. Design of a 147-level cascade inverter (based on the CAPUC1) and a novel 49-level modified structure are analyzed under optimal number of DC sources and power switches. Finally, experimental validations were performed by implementing laboratory prototypes. Experimental results in steady state and dynamics conditions showed that the proposed structures can generate output voltage with the lowest THD and highest controllability.

REFERENCES:

[1] H. Akagi, "Classification, Terminology, and Application of the Modular Multilevel Cascade Converter (MMCC)," in IEEE Transactions on Power Electronics, vol. 26, no. 11, pp. 3119-3130, Nov. 2011.

[2] S. Kouro et al., "Recent Advances and Industrial Applications of Multilevel Converters," in IEEE Transactions on Industrial Electronics, vol. 57, no. 8, pp. 2553-2580, Aug. 2010.

[3] J. Rodriguez, S. Bernet, B. Wu, J. O. Pontt and S. Kouro, "Multilevel Voltage-Source-Converter Topologies for Industrial Medium-Voltage Drives," in IEEE Transactions on Industrial Electronics, vol. 54, no. 6, pp. 2930-2945, Dec. 2007.

[4] H. Abu-Rub, J. Holtz, J. Rodriguez and G. Baoming, "Medium-Voltage Multilevel Converters—State of the Art, Challenges, and Requirements in Industrial Applications," in IEEE Transactions on Industrial Electronics, vol. 57, no. 8, pp. 2581-2596, Aug. 2010.

[5] X. Zha, L. Xiong, J. Gong and F. Liu, "Cascaded multilevel converter for medium-voltage motor drive capable of regenerating with part of cells," in IET Power Electronics, vol. 7, no. 5, pp. 1313-1320, May 2014.

Low Switching Frequency Based Asymmetrical Multilevel Inverter Topology With Reduced Switch Count

 ABSTRACT:

 The inceptions of multilevel inverters (MLI) have caught the attention of researchers for medium and high power applications. However, there has always been a need for a topology with a lower number of device count for higher efficiency and reliability. A new single-phase MLI topology has been proposed in this paper to reduce the number of switches in the circuit and obtain higher voltage level at the output. The basic unit of the proposed topology produces 13 levels at the output with three dc voltage sources and eight switches. Three extentions of the basic unit have been proposed in this paper. A detailed analysis of the proposed topology has been carried out to show the superiority of the proposed converter with respect to the other existing MLI topologies. Power loss analysis has been done using PLECS software, resulting in a maximum ef_ciency of 98.5%. Nearest level control (NLC) pulse-width modulation technique has been used to produce gate pulses for the switches to achieve better output voltage waveform. The various simulation results have been performed in the PLECS software and a laboratory setup has been used to show the feasibility of the proposed MLI topology.

KEYWORDS:

1.      DC - AC converter

2.      Multilevel inverter

3.      Reduce switch count

4.       Nearest level control (NLC)

SOFTWARE: MATLAB/SIMULINK

CONCLUSION:   

The paper presents a novel MLI topology with multiple exten- sion capabilities. The basic unit of the proposed topology produces 13 levels using eight unidirectional switches and three dc voltage sources. Three different extension of the basic unit has been proposed. The performance analysis of the basic unit of the proposed topology has been done and the comparative results with some recently proposed topologies in literature have been presented in the paper. Further, a power loss analysis of the dynamic losses (switching and conduction) in the MLI has also been presented, which gives the maximum efficicnecy of the basic unit as 98.5%. The power loss distribution in all the switches for different combination of loads have also been demonstrated in the paper. The performance of the proposed topology has been simulated with dynamic modulation indexes and different combination of loads using PLECS software. A prototype of the basic unit has been developed in the laboratory and the simulation results have been validated using the different expriemntal results considering different modulation indexes.

REFERENCES:

[1] S. Kouro, M. Malinowski, K. Gopakumar, J. Pou, L. G. Franquelo, B.Wu, J. Rodriguez, M. A. Perez, and J. I. Leon, ``Recent advances and industrial applications of multilevel converters,'' IEEE Trans. Ind. Electron., vol. 57, no. 8, pp. 2553_2580, Aug. 2010.

[2] H. Aburub, J. Holtz, and J. Rodriguez, ``Medium-voltage multilevel converters-state of the art, challenges, and requirements in industrial applications,'' IEEE Trans. Ind. Electron, vol. 57, no. 8, pp. 2581_2596, Dec. 2010.

[3] H. Akagi, ``Multilevel converters: Fundamental circuits and systems,'' Proc. IEEE, vol. 105, no. 11, pp. 2048_2065, Nov. 2017.

[4] J. I. Leon, S. Vazquez, and L. G. Franquelo, ``Multilevel converters: Control and modulation techniques for their operation and industrial appli- cations,'' Proc. IEEE, vol. 105, no. 11, pp. 2066_2081, Nov. 2017.

[5] J. Venkataramanaiah, Y. Suresh, and A. K. Panda, ``A review on symmet- ric, asymmetric, hybrid and single DC sources based multilevel inverter topologies,'' Renew. Sustain. Energy Rev., vol. 76, pp. 788_812, Sep. 2017.

Fast Sensor-Less Voltage Balancing and Capacitor Size Reduction in PUC5 Converter Using Novel Modulation Method

ABSTRACT:

 This paper proposes a novel sensor-less switching method based on logic gates for five-level packed U-cell (PUC5) converter. It comprises only two level-shifted triangular carriers and logic gates. Hence, the number of triangular carriers is halved and the switching states table is eliminated, which cause remarkable reduction in complexity of the proposed modulation method. Moreover, employing the proposed sensor-less switching method leads to decrease in the PUC5 capacitor value by factor of carrier ratio, fast self-balancing of the PUC5 capacitor voltage, and halving the output LC filter inductor and capacitor values in stand-alone mode as well as the grid link inductor value in grid connected mode. In addition, the PUC5 converter start-up transient time is considerably decreased and the first switching harmonic cluster frequency is doubled, which lead to notable improvement of steady-state and dynamic performance of the PUC5 converter. The proposed sensor-less switching method has been implemented in both stand-alone and grid-connected operating modes of PUC5 converter. Provided simulation and experimental results verify the feasibility and effectiveness of the proposed sensor-less switching method as well as its improved dynamic and steady state performances in both stand-alone and grid-connected modes.

KEYWORDS:

 

1.      Capacitor size reduction

2.      Logic gate based modulation method

3.      Multilevel inverter

4.      Packed U-cell (PUC)

5.      Sensor-less control

SOFTWARE: MATLAB/SIMULINK

CONCLUSION:  

In this paper, a novel sensor-less switching method based on logic gates was proposed for PUC5 converter. It comprises only two level shifted triangular carriers and logic form equations and does not have switching states table. Hence, the proposed method does not compel complex calculations and can be easily implemented on low-cost microcontrollers. By utilizing the proposed sensor-less modulation method, the charging and discharging of capacitor is balanced in each switching period, which causes fast self-balancing of the PUC5 capacitor voltage. Moreover, employing the proposed sensor-less switching method leads to decrease the PUC5 capacitor value by factor of carrier ratio ( 0 SW C F R F = ), and halving the output LC filter inductor and capacitor sizes in stand-alone mode as well as the grid link inductor size in gridconnected mode. In addition, the PUC5 converter start-up transient time is considerably decreased and the first switching harmonic cluster frequency is doubled, which lead to notable improvement of steady-state and dynamic performance of PUC5 converter. The proposed sensor-less switching method has been evaluated for both stand-alone and grid-connected modes. An external current controller has been used to control the injected active and reactive power to the grid. Provided simulation and experimental results for stand-alone and gridconnected gridconnected modes verify the feasibility and effectiveness of the proposed sensor-less switching method as well as its improved dynamic and steady state performance.

REFERENCES:

[1] J. Li, S. Bhattacharya, and A. Q. Huang, "A New Nine-Level Active NPC (ANPC) Converter for Grid Connection of Large Wind Turbines for Distributed Generation," IEEE Trans. Power Electron., vol. 26, pp. 961-972, 2011.

[2] M. Abarzadeh, H. M. Kojabadi, and L. Chang, "A Modified Static Ground Power Unit Based on Novel Modular Active Neutral Point Clamped Converter," IEEE Trans. Ind. Appl., vol. 52, pp. 4243-4256, 2016.

[3] M. Abarzadeh, H. M. Kojabadi, F. Deng, and Z. Chen, "Enhanced static ground power unit based on flying capacitor based h-bridge hybrid active-neutral-point-clamped converter," IET Power Electron., vol. 9, pp. 2337-2349, 2016.

[4] S. Kouro, M. Malinowski, K. Gopakumar, J. Pou, L. G. Franquelo, B. Wu, et al., "Recent Advances and Industrial Applications of Multilevel Converters," IEEE Trans. Ind. Electron., vol. 57, pp. 2553-2580, 2010.

[5] J. Rodriguez, S. Bernet, B. Wu, J. O. Pontt, and S. Kouro, "Multilevel Voltage-Source-Converter Topologies for Industrial Medium-Voltage Drives," IEEE Trans. Ind. Electron., vol. 54, pp. 2930-2945, 2007.

Evaluation of Level-Shifted and Phase-Shifted PWM Schemes for Seven Level Single-Phase Packed U Cell Inverter

 ABSTRACT:

 An evaluation of level shifted and phase shifted triangular and sawtooth carrier modulation schemes for a seven level packed U cell (PUC) inverter is presented in this paper. The investigated PUC is the recently introduced topology for multilevel inverter having reduced switch count in comparison to the conventional topologies of multilevel inverters. The PUC inverter has six switches for 7 level inverter which is very less in comparison to the conventional topologies. In this paper, the level-shifted pulse width modulation (LS-PWM) and phase-shifted PWM (PS-PWM) for triangular and sawtooth carrier are presented and compared. A comparative harmonic analysis for all the cases is performed and results are presented in the paper. The difference in harmonics of the two modulation methods given by the theoretical approach for both the carrier is validated by the experimental results. DC voltage controller and load current controller of the PUC inverter are also designed and presented. The investigated PUC topology is tested in dynamic and steady state conditions and results obtained are presented. The analysis is done and validated using simulation in MATLAB® Simulink environment and experimental approaches using FPGA platform.

KEYWORDS:

1.      Level shift

2.       Multilevel inverter

3.       Modulation

4.      Phase shift

5.       PI controller

6.      PUC inverter

SOFTWARE: MATLAB/SIMULINK

CONCLUSION:  

The paper has presented the comparison of different PWM schemes which can be applied to the PUC inverter. Investigating the suitable modulation schemes is very essential with respect to local grid integration, as the power quality is directly dependent on THD. Triangular carrier based PWM schemes is exhibiting the better result than the sawtooth carrier based PWM schemes as the triangular level shifted carrier PWM scheme is better as compared to sawtooth level shifted carrier because in triangular level shifted carrier both edges (falling and rising) of pulses are modulated which improves the harmonic spectrum. However, in the sawtooth level shifted carrier only rising edges are modulated. Hence triangular level shifted carrier PWM scheme can be applied for integrating the PUC inverter with PV and local grid systems. Triangular level shifted carrier PWM scheme for PUC inverter has been suggested based on observing the THD in voltage and current which are respectively just 17.92% and 2.43%. The whole system i.e. solar panel, boost converter with PUC inverter will be very cost effective, besides having good  reliability and power quality as it has the minimum number of power electronics devices compared to previously introduced multilevel inverter topologies. With reduced number of capacitors and power switches seven levels of voltages have been achieved for PUC inverter.

REFERENCES:

[1] F. A. Rahman, M. M. A. Aziz, R. Saidur, W. A. A. Bakar, M. R. Hainin, R. Putrajaya, and N. A. Hassan, “Pollution to solution: Capture and sequestration of carbon dioxide (CO2) and its utilization as a renewable energy source for a sustainable future”, Renewable and Sustainable Energy Reviews,vol. 71, pp. 112-126, May 2017.

[2] Y. Yang, A. Sangwongwanich, and F. Blaabjerg, “Design for reliability of power electronics for grid-connected photovoltaic systems,” in CPSS Transactions on Power Electronics and Applications, vol. 1, no. 1, pp. 92-103, Dec. 2016..

[3] J. Rodriguez, J.-S. Lai, and F. Z. Peng, “Multilevel inverters: a survey of topologies, controls, and applications,” Industrial Electronics, IEEE Transactions on, vol. 49, pp. 724-738, 2002.

[4] Q. M. Attique, Y. Li, and K. Wang, “A survey on space-vector pulse width modulation for multilevel inverters,” in CPSS Transactions on Power Electronics and Applications, vol. 2, no. 3, pp. 226-236, Sept. 2017.

[5] Z. Mohzani, B. P. McGrath, and D. G. Holmes, “A generalized natural balance model and balance booster filter design for three-level Neutral- Point-Clamped converters,” in IEEE Transactions on Industry Applications, vol. 51, no. 6, pp. 4605-4613, Nov.-Dec. 2015.