Packed E-Cell (PEC) Converter TopologyOperation and Experimental Validation

ABSTRACT:

 

This paper proposes a novel single-dc-source multilevel inverter called Packed E-Cell (PEC) topology to achieve nine levels with noticeably reduced components count, while dc capacitors are actively balanced. The nine-level PEC (PEC9) is composed of seven active switches and two dc capacitors that are shunted by a four-quadrant switch to from the E-cell, and it makes use of a single dc link. With the proper design of the corresponding PEC9 switching states, the dc capacitors are balanced using the redundant charging/discharging states. Since the shunted capacitors are horizontally extended, both capacitors are simultaneously charged or discharged with the redundant states, so only the auxiliary dc-link voltage needs to be sensed and regulated to half of the input dc source voltage, and consequently, dc capacitors' voltages are inherently balanced to one quarter of the dc bus voltage. To this end, an active capacitor voltage balancing integrated to the level-shifted half-parabola carrier PWM technique has been designed based on the redundant charging/discharging states to regulate the dc capacitors voltages of PEC9. Furthermore, using the E-cell not only reduces components count but also the proposed topology permits multi ac terminal operation. Thus, Five-level inverter operation can be achieved during the four-quadrant switch fault, which confers to the structure high reliability. The theoretical analysis as well as the experimental results are presented and discussed, showing the basic operation, multi-functionality, as well as the superior performance of the proposed novel PEC9 inverter topology.

 KEYWORDS:

 

1.      Nine-level Packed E-Cell (PEC)

2.      Single-dc source inverter

3.      Single auxiliary dc-link capacitors

4.       Multilevel converter

5.      PUC converter

6.       Active rectifier

7.      Active filter

8.      Grid-connected converter

SOFTWARE: MATLAB/SIMULINK

CONCLUSION:

In this paper, a novel nine-level single-DC source Packed E-Cell (PEC9) topology has been introduced as a promising candidate for single-phase inverter suitable for symmetrical and asymmetrical series of connection. The presented structure is indeed an optimized compact design topology which permits the reduction of auxiliary DC-link and components count by using E-Cell type of connection. Moreover, by horizontal extension of auxiliary DC-link, in the form of E-Cells, simultaneous charging or discharging with redundant state are achieved that guarantees floating capacitors voltage balancing under all operating conditions. An active voltage balancing algorithm was integrated to the half parabola carrier PWM based technique to efficiently regulate floating capacitors voltages. It was also demonstrated that different output stepped voltage waveforms are achievable without changing in converter circuit design. The presented experimental results of PEC9 validated its reliable performance in keeping capacitors voltages balanced under different load and source conditions that can emerge as a competitive topology for various industrial standalone and grid-tied applications.

REFERENCES:

[1] M. Norambuena, S. Kouro, S. Dieckerhoff, and J. Rodriguez, ``Reduced multilevel converter: A novel multilevel converter with a reduced number of active switches,'' IEEE Trans. Ind. Electron., vol. 65, no. 5, pp. 3636_3645, May 2018.

[2] H. Vahedi, A. A. Shojaei, L.-A. Dessaint, and K. Al-Haddad, ``Reduced DC-link voltage active power _lter using modi_ed PUC5 converter,'' IEEE Trans. Power Electron., vol. 33, no. 2, pp. 943_947, Feb. 2018.

[3] H. Aburub, J. Holtz, and J. Rodriguez, ``Medium-voltage multilevel converters-state of the art, challenges, and requirements in industrial applications,'' IEEE Trans. Ind. Electron, vol. 57, no. 8, pp. 2581_2596, Dec. 2010.

[4] N. Arun and M. M. Noel, ``Crisscross switched multilevel inverter using cascaded semi-half-bridge cells,'' IET Power Electron., vol. 11, no. 1, pp. 23_32, Jan. 2017.

[5] E. Babaei and S. Laali, ``Optimum structures of proposed new cascaded multilevel inverter with reduced number of components,'' IEEE Trans. Ind. Electron., vol. 62, no. 11, pp. 6887_6895, Nov. 2015.