Multilevel Inverter Topologies with ReducedDevice Count: A Review

 

ABSTRACT:

 Multilevel inverters have created a new wave of interest in industry and research. While the classical topologies have proved to be a viable alternative in a wide range of highpower medium-voltage applications, there has been an active interest in the evolution of newer topologies. Reduction in overall part count as compared to the classical topologies has been an important objective in the recently introduced topologies. In this paper, some of the recently proposed multilevel inverter topologies with reduced power switch count are reviewed and analysed. The paper will serve as an introduction and an update to these topologies, both in terms of the qualitative and quantitative parameters. Also, it takes into account the challenges which arise when an attempt is made to reduce the device count. Based on a detailed comparison of these topologies as presented in this paper, appropriate multilevel solution can be arrived at for a given application.

KEYWORDS:

1.      Multilevel inverters

2.      Reduced device count

3.      Even power distribution

4.       Fundamental switching frequency operation

5.      Source configuration

SOFTWARE: MATLAB/SIMULINK

CONCLUSION:  

As multilevel inverters continue to gain increasing importance for both high power and low power applications, many researchers have proposed specific topological solutions for intended applications. Also, newer multilevel topologies have been proposed, offering high output resolution with a reduced number of power switches. In this paper, a review of nine reduced device count multilevel topologies is presented. Based on the review, it can be concluded that in the process of reducing the power switch count, various compromises are involved such as:

i. Increased voltage rating of semiconductor switches.

ii. Requirement of bidirectional switches

iii. Increased number of sources and/or requirement of asymmetric input DC levels.

iv. Loss of modularity.

v. Reduced number of redundant states.

vi. Complex modulation / control schemes.

vii. Difficulty in possibility of charge balance control.

In this paper, qualitative and quantitative features of RDC-MLI topologies have been discussed and a comparison has been made so as to facilitate a well-informed selection of topology for a given application. In addition, the paradigm presented in the paper will also help to evaluate the RDC-MLI topologies that will be proposed in future.

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