Modified Multilevel Inverters with Reduced Structures Based on Packed U-Cell

 ABSTRACT:

 Multilevel inverters are capable of generating high-quality staircase pseudo-sinusoidal voltage waveform with low THD. These types of topologies may require large number of switches and power supplies. This leads to higher cost and volume of the converter along with complicated control algorithms. Recently, a branch of multilevel converters is emerged as compact power conversion units, in which their ‘reduced-structure’ topologies use lower number of active and passive devices compared with the available topologies. Packed U-Cell, a new reduced-structure multilevel converter, has been recently reported in the literature to reduce component count. Packed U-Cell requires lesser active switches as compared to the existing counterparts. However, there are some drawbacks associated with this topology such as restricted maximum output voltage, high voltage stress on switches, and limited performance to low voltage applications. Available literature present generalization of the topology with special asymmetrical source-ratio, but no sufficient and effective investigations have been made for modified structures or other symmetrical or asymmetrical source-ratio with cascaded configurations. In this paper, the issues associated with PUC are addressed and two approaches as remedy are presented. The first approach presents a comprehensive analysis of cascaded topologies with the proposed basic units, and the second approach is related to a new modified configuration on the basis of the conventional converter for improving the performance of the PUC in terms of total blocking voltage, switch ratings and extending its performance to high voltage applications. Moreover, design of a novel 49-level modified structure and 147-level cascade inverter based on conventional PUC are analyzed under optimal number of DC sources and power switches to get the best possible topology as a solution. Finally, experimental validations were performed by implementing laboratory prototypes.

KEYWORDS:

 

1.      Asymmetrical DC Sources

2.      Multilevel inverter

3.      Modified structure

4.      Packed U-Cell

5.      Reduced structures

SOFTWARE: MATLAB/SIMULINK

CONCLUSION:   

In this paper different drawbacks associated with a newly introduced multilevel converter, named as Packed U-Cell (PUC), such as restricted maximum output voltage, high voltage stress on switches, and limited performance to low voltage applications, are presented. For solving these drawbacks, no sufficient investigations in literature have been made as modified structures or other symmetrical or asymmetrical cascaded configurations. The motivation for conducting this study is to achieve more voltage levels with reduction in the number of power electronics components with lower ratings and blocking voltages, and extending its performance to high voltage applications, using cascaded (approach 1) or modified (approach 2) structures. In the first approach, analysis showed that with using only two DC sources in each cascaded module (..=2), the CAPUC1 and CAPUC2 generate the maximum number of voltage levels with a fixed number of DC sources and switches. Using more than two DC sources in each module, the CAPUC1 generates more voltage levels. Consequently, the CAPUC1 has the optimal structure among all discussed cascade structures. In the second one, the proposed modified structure can improve conventional PUC performance based on power switch ratings for high power applications. Design of a 147-level cascade inverter (based on the CAPUC1) and a novel 49-level modified structure are analyzed under optimal number of DC sources and power switches. Finally, experimental validations were performed by implementing laboratory prototypes. Experimental results in steady state and dynamics conditions showed that the proposed structures can generate output voltage with the lowest THD and highest controllability.

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