Real-Time Implementation of a 31-Level Asymmetrical Cascaded Multilevel Inverter for Dynamic Loads

 ABSTRACT:

Among the renewable energy applications, the most popular inverters are cascaded multilevel inverters. Irrespective of numerous benefits these inverters face reliability issues due to the presence of more circuit components in the design. This has been a critical challenge for researchers in designing inverters with enhanced reliability by reducing the total harmonic distortion (THD). This paper proposes a 31-level asymmetric cascaded multilevel inverter for renewable energy applications. The proposed topology produces waveforms consisting of the staircase with a high number of output levels with lesser components with low THD. The investigations on the feasibility and performance of MLI under steady-state, transient, and dynamic load disturbances. The results are validated from a 1.6kW system which provides the proposed inverter.

KEYWORDS:

1.      Multilevel inverter (MLI)

2.       total harmonic distraction (THD)

3.       staircase modulation technique

SOFTWARE: MATLAB/SIMULINK

CONCLUSION:  

The proposed inverter is tested experimentally with resistive and inductive loads. The output waveforms obtained during the resistive load test clearly show that the phase angle between current and voltage is zero. And the inductive load testing results show that the current is lagging voltage. To test the robustness of the proposed scheme, a load disturbances test is conducted. It is observed that the proposed topology is well stabilized under load disturbances conditions. The presented topology provides seven-level and thirty-one level output voltage with only 6 and 10 switches respectively in asymmetrical conditions. Under simulation a THD value of 3.62% is obtained using SIMULINK. under experimental conditions the computed THD value is 3.7%. The ability of presented MLI topology has been veri_ed using both simulation and experimental setups and the results are demonstrated for both conditions. The suggested topology is appropriate for the integration of medium-voltage renewable energy and power quality improvement in DVR, DStatcom and FACTs.

REFERENCES:

[1] T. Porselvi and R. Muthu, ``Comparison of cascaded H-Bridge, neutral point clamped and _ying capacitor multilevel inverters using multicarrier PWM,'' in Proc. Annu. IEEE India Conf., Dec. 2011, pp. 1_4.

[2] M. A. Hosseinzadeh, M. Sarbanzadeh, E. Sarbanzadeh, M. Rivera, and R. Grégor, ``Back-to-back modi_ed T-type half-bridge module for cascaded multi-level inverters with decreased number of components,'' in Proc. IEEE Int. Conf. Electr. Syst. Aircraft, Railway, Ship Propuls. Road Vehicles Int. Transp. Electri_c. Conf. (ESARS-ITEC), Nov. 2018, pp. 1_6.

[3] J. Rodríguez, J.-S. Lai, and F. Z. Peng, ``Multilevel inverters: A survey of topologies, controls, and applications,'' IEEE Trans. Ind. Electron., vol. 49, no. 4, pp. 724_738, Aug. 2002.

[4] Y. Suresh, J. Venkataramanaiah, A. K. Panda, C. Dhanamjayulu, and P. Venugopal, ``Investigation on cascade multilevel inverter with symmetric, asymmetric, hybrid and multi-cell con_gurations,'' Ain Shams Eng. J., vol. 8, no. 2, pp. 263_276, 2017.

[5] N. Prabaharan, A. H. Fathima, and K. Palanisamy, ``New hybrid multilevel inverter topology with reduced switch count using carrier based pulse width modulation technique,'' in Proc. IEEE Conf. Energy Convers. (CENCON), Oct. 2015, pp. 176_180.

PWM Sensor-less Balancing Technique for theFifteen-Level PUC Converter

 ABSTRACT:

In this paper, a novel PWM technique insuring the self-balancing of the capacitors voltages has been proposed for the attained nine-level packed U cells (PUC) converter. In the traditional fifteen-level operation, the capacitors voltages have to be maintained around their references using a state variable feedback which requires three sensors, two for the capacitors voltages and one for the load current. By applying the proposed PWM technique to the fifteen-level PUC converter, self balancing of the capacitors voltages is attained, which results in the proposed nine-level converter. The proposed balancing technique is achieved without any closed loop regulation or sensors. The proposed concept has been verified by mean of simulations performed in the Matlab Simulink environments. Simulation results show that even under severe DC bus voltage and load parameters variations, the capacitors voltages remains around their required values. Harmonics contents of load current depend on the modulating signal frequency. Moreover, even under low frequencies, the total harmonics distortion remains reduced.

KEYWORDS:

1.      Packed U cells

2.      Multilevel converters

3.      Self balancing

4.      PWM technique

SOFTWARE: MATLAB/SIMULINK

CONCLUSION:  

A sensor-less self balancing PWM technique applied to the fifteen-level PUC inverter was presented in this paper. It allows a fast open loop regulation of the PUC inverter capacitors voltages without using any additional circuit. Indeed, the self balancing is achieved without using any state variable feedback or sensors. The proposed concept was verified by simulation results.

REFERENCES:

[1] Y. Ounejjar and K. Al-Haddad "A novel high energetic efficiency multilevel topology with reduced impact on supply network", The 34^th Annual Conference of the IEEE Industrial Electronics Society, pp.489-494, 10-13 November 2008, Orlando, Florida, USA

[2]- Ounejjar, Y., K. Al-Haddad et L. Gregoire.. "Packed U Cells Multilevel Converter Topology: Theoretical Study and Experimental Validation". IEEE Transactions on Industrial Electronics, vol. 58, n°4, p.1294-1306, (April 2011).

[3] X. h. Zhang and W. k. Yue, "Neutral point potential balance algorithm for three-level NPC inverter based on SHEPWM," in Electronics Letters,vol. 53, no. 23, pp. 1542-1544, 11 9 2017

[4] M. Sleiman, K. Al-Haddad, H. F. Blanchette and H. Y. Kanaan, "Insertion Index Generation Method Using Available Leg–Average Voltage to Control Modular Multilevel Converters," in IEEE Transactions on Industrial Electronics, vol. PP, no. 99, pp. 1-1.

[5] I. López et al., "Modulation Strategy for Multiphase Neutral-Point- Clamped Converters," in IEEE Transactions on Power Electronics, vol. 31, no. 2, pp. 928-941, Feb. 2016.

Multilevel Inverter Topologies with ReducedDevice Count: A Review

 

ABSTRACT:

 Multilevel inverters have created a new wave of interest in industry and research. While the classical topologies have proved to be a viable alternative in a wide range of highpower medium-voltage applications, there has been an active interest in the evolution of newer topologies. Reduction in overall part count as compared to the classical topologies has been an important objective in the recently introduced topologies. In this paper, some of the recently proposed multilevel inverter topologies with reduced power switch count are reviewed and analysed. The paper will serve as an introduction and an update to these topologies, both in terms of the qualitative and quantitative parameters. Also, it takes into account the challenges which arise when an attempt is made to reduce the device count. Based on a detailed comparison of these topologies as presented in this paper, appropriate multilevel solution can be arrived at for a given application.

KEYWORDS:

1.      Multilevel inverters

2.      Reduced device count

3.      Even power distribution

4.       Fundamental switching frequency operation

5.      Source configuration

SOFTWARE: MATLAB/SIMULINK

CONCLUSION:  

As multilevel inverters continue to gain increasing importance for both high power and low power applications, many researchers have proposed specific topological solutions for intended applications. Also, newer multilevel topologies have been proposed, offering high output resolution with a reduced number of power switches. In this paper, a review of nine reduced device count multilevel topologies is presented. Based on the review, it can be concluded that in the process of reducing the power switch count, various compromises are involved such as:

i. Increased voltage rating of semiconductor switches.

ii. Requirement of bidirectional switches

iii. Increased number of sources and/or requirement of asymmetric input DC levels.

iv. Loss of modularity.

v. Reduced number of redundant states.

vi. Complex modulation / control schemes.

vii. Difficulty in possibility of charge balance control.

In this paper, qualitative and quantitative features of RDC-MLI topologies have been discussed and a comparison has been made so as to facilitate a well-informed selection of topology for a given application. In addition, the paradigm presented in the paper will also help to evaluate the RDC-MLI topologies that will be proposed in future.

REFERENCES:

[1] Espinoza, J. R.;, "Inverters," Power Electronics Handbook, MH Rashid (Ed.), pp. 225-269, 2001.

[2] Abbott, D.;, "Keeping the Energy Debate Clean: How Do We Supply the World's Energy Needs?," Proceedings of the IEEE , vol.98, no.1, pp.42-66, Jan. 2010.

[3] Xinghuo, Y.; Cecati, C.; Dillon, T.; SimoÞes, M.G.;, "The New Frontier of Smart Grids," Industrial Electronics Magazine, IEEE , vol.5, no.3, pp.49-63, Sept. 2011.

[4] Daher, S.;,“ Analysis, design and implementation of a high efficiency multilevel converter for renewable energy systems” , PhD Dissertation Submitted to Kassel University, Kassel, Germany, 2006, Available: http://www.uni-kassel.de/upress/online/frei/978-3-89958-236-9.volltext.frei.pdf.

[5] Franquelo, L.G.; Rodriguez, J.; Leon, J.I.; Kouro, S.; Portillo, R.; Prats, M.A.M.; , "The age of multilevel converters arrives," Industrial Electronics Magazine, IEEE , vol.2, no.2, pp.28-39, June 2008.

Modified Seven-Level Pack U-Cell Inverter forPhotovoltaic Applications

 ABSTRACT:

 This paper proposes a modified configuration of single-phase Pack U-Cell (PUC) multilevel inverter in which the output voltage has higher amplitude than the maximum DC link value used in the topology as a boost operation. The introduced inverter generates seven-level AC voltage at the output using two DC links and six semiconductor switches. Comparing to cascaded H-bridge and neutral point clamp multilevel inverters, the introduced multilevel inverter produces more voltage levels using less components. The proposed inverter is used in PV system where the green power comes from two separate PV panels connected to the DC links through DC-DC converters to draw the maximum power. Due to boost operation of this inverter, two different PV panels can combine and send their powers to the grid. Simulations and experimental tests are conducted to investigate the good dynamic performance of the inverter in grid-connected PV system.

 KEYWORDS:

1.      PV Inverter

2.      Pack U-Cell

3.      Modified Pack U-Cell

4.      PUC5

5.       MPUC5

6.      Power Quality

7.       Renewable Energy Conversion

SOFTWARE: MATLAB/SIMULINK

CONCLUSION:  

In this paper a modified multilevel inverter topology has been presented. The proposed MPUC inverter can generate 7-level voltage waveform at the output with low harmonic contents. Unlike the reported PUC topology, the 7-level MPUC inverter is capable to produce voltage levels more than the DC sources used in the structure. It can sum up the DC buses amplitudes to deliver more power to the output. The associated switching algorithm has been designed and implemented on the introduced MPUC topology with reduced switching frequency aspect. Moreover, photovoltaic application has been targeted for this inverter to deliver power from PV panels with different voltage/current rating to grid. In this regard, results have been shown to validate the acceptable voltage regulation and current controlling of the grid-connected inverter as well as the implemented P&O MPPT algorithm.

REFERENCES:

[1] B. Singh, A. Chandra, and K. Al-Haddad, Power Quality: Problems and Mitigation Techniques: John Wiley & Sons, 2014.

[2] I. Gowaid, G. Adam, A. Massoud, S. Ahmed, and B. Williams, "Hybrid and Modular Multilevel Converter Designs for Isolated HVDC-DC Converters," IEEE Journal Emerg. and Select. Topics in Power Electron., vol. PP, no. 99, p. 1, 2017.

[3] H. Vahedi, K. Al-Haddad, Y. Ounejjar, and K. Addoweesh, "Crossover Switches Cell (CSC): A New Multilevel Inverter Topology with Maximum Voltage Levels and Minimum DC Sources," in IECON 2013-39th Annual Conference on IEEE Industrial Electronics Society, Austria, 2013, pp. 54-59.

[4] P. W. Hammond, "A new approach to enhance power quality for medium voltage drives," in Petroleum and Chemical Industry Conference, 1995. Record of Conference Papers., Industry Applications Society 42nd Annual, 1995, pp. 231-235.

[5] A. Nabae, I. Takahashi, and H. Akagi, "A new neutral-point-clamped PWM inverter," IEEE Trans. Ind. Applications, no. 5, pp. 518-523, 1981.

Packed E-Cell (PEC) Converter TopologyOperation and Experimental Validation

ABSTRACT:

 

This paper proposes a novel single-dc-source multilevel inverter called Packed E-Cell (PEC) topology to achieve nine levels with noticeably reduced components count, while dc capacitors are actively balanced. The nine-level PEC (PEC9) is composed of seven active switches and two dc capacitors that are shunted by a four-quadrant switch to from the E-cell, and it makes use of a single dc link. With the proper design of the corresponding PEC9 switching states, the dc capacitors are balanced using the redundant charging/discharging states. Since the shunted capacitors are horizontally extended, both capacitors are simultaneously charged or discharged with the redundant states, so only the auxiliary dc-link voltage needs to be sensed and regulated to half of the input dc source voltage, and consequently, dc capacitors' voltages are inherently balanced to one quarter of the dc bus voltage. To this end, an active capacitor voltage balancing integrated to the level-shifted half-parabola carrier PWM technique has been designed based on the redundant charging/discharging states to regulate the dc capacitors voltages of PEC9. Furthermore, using the E-cell not only reduces components count but also the proposed topology permits multi ac terminal operation. Thus, Five-level inverter operation can be achieved during the four-quadrant switch fault, which confers to the structure high reliability. The theoretical analysis as well as the experimental results are presented and discussed, showing the basic operation, multi-functionality, as well as the superior performance of the proposed novel PEC9 inverter topology.

 KEYWORDS:

 

1.      Nine-level Packed E-Cell (PEC)

2.      Single-dc source inverter

3.      Single auxiliary dc-link capacitors

4.       Multilevel converter

5.      PUC converter

6.       Active rectifier

7.      Active filter

8.      Grid-connected converter

SOFTWARE: MATLAB/SIMULINK

CONCLUSION:

In this paper, a novel nine-level single-DC source Packed E-Cell (PEC9) topology has been introduced as a promising candidate for single-phase inverter suitable for symmetrical and asymmetrical series of connection. The presented structure is indeed an optimized compact design topology which permits the reduction of auxiliary DC-link and components count by using E-Cell type of connection. Moreover, by horizontal extension of auxiliary DC-link, in the form of E-Cells, simultaneous charging or discharging with redundant state are achieved that guarantees floating capacitors voltage balancing under all operating conditions. An active voltage balancing algorithm was integrated to the half parabola carrier PWM based technique to efficiently regulate floating capacitors voltages. It was also demonstrated that different output stepped voltage waveforms are achievable without changing in converter circuit design. The presented experimental results of PEC9 validated its reliable performance in keeping capacitors voltages balanced under different load and source conditions that can emerge as a competitive topology for various industrial standalone and grid-tied applications.

REFERENCES:

[1] M. Norambuena, S. Kouro, S. Dieckerhoff, and J. Rodriguez, ``Reduced multilevel converter: A novel multilevel converter with a reduced number of active switches,'' IEEE Trans. Ind. Electron., vol. 65, no. 5, pp. 3636_3645, May 2018.

[2] H. Vahedi, A. A. Shojaei, L.-A. Dessaint, and K. Al-Haddad, ``Reduced DC-link voltage active power _lter using modi_ed PUC5 converter,'' IEEE Trans. Power Electron., vol. 33, no. 2, pp. 943_947, Feb. 2018.

[3] H. Aburub, J. Holtz, and J. Rodriguez, ``Medium-voltage multilevel converters-state of the art, challenges, and requirements in industrial applications,'' IEEE Trans. Ind. Electron, vol. 57, no. 8, pp. 2581_2596, Dec. 2010.

[4] N. Arun and M. M. Noel, ``Crisscross switched multilevel inverter using cascaded semi-half-bridge cells,'' IET Power Electron., vol. 11, no. 1, pp. 23_32, Jan. 2017.

[5] E. Babaei and S. Laali, ``Optimum structures of proposed new cascaded multilevel inverter with reduced number of components,'' IEEE Trans. Ind. Electron., vol. 62, no. 11, pp. 6887_6895, Nov. 2015.

Modified Multilevel Inverters with Reduced Structures Based on Packed U-Cell

 ABSTRACT:

 Multilevel inverters are capable of generating high-quality staircase pseudo-sinusoidal voltage waveform with low THD. These types of topologies may require large number of switches and power supplies. This leads to higher cost and volume of the converter along with complicated control algorithms. Recently, a branch of multilevel converters is emerged as compact power conversion units, in which their ‘reduced-structure’ topologies use lower number of active and passive devices compared with the available topologies. Packed U-Cell, a new reduced-structure multilevel converter, has been recently reported in the literature to reduce component count. Packed U-Cell requires lesser active switches as compared to the existing counterparts. However, there are some drawbacks associated with this topology such as restricted maximum output voltage, high voltage stress on switches, and limited performance to low voltage applications. Available literature present generalization of the topology with special asymmetrical source-ratio, but no sufficient and effective investigations have been made for modified structures or other symmetrical or asymmetrical source-ratio with cascaded configurations. In this paper, the issues associated with PUC are addressed and two approaches as remedy are presented. The first approach presents a comprehensive analysis of cascaded topologies with the proposed basic units, and the second approach is related to a new modified configuration on the basis of the conventional converter for improving the performance of the PUC in terms of total blocking voltage, switch ratings and extending its performance to high voltage applications. Moreover, design of a novel 49-level modified structure and 147-level cascade inverter based on conventional PUC are analyzed under optimal number of DC sources and power switches to get the best possible topology as a solution. Finally, experimental validations were performed by implementing laboratory prototypes.

KEYWORDS:

 

1.      Asymmetrical DC Sources

2.      Multilevel inverter

3.      Modified structure

4.      Packed U-Cell

5.      Reduced structures

SOFTWARE: MATLAB/SIMULINK

CONCLUSION:   

In this paper different drawbacks associated with a newly introduced multilevel converter, named as Packed U-Cell (PUC), such as restricted maximum output voltage, high voltage stress on switches, and limited performance to low voltage applications, are presented. For solving these drawbacks, no sufficient investigations in literature have been made as modified structures or other symmetrical or asymmetrical cascaded configurations. The motivation for conducting this study is to achieve more voltage levels with reduction in the number of power electronics components with lower ratings and blocking voltages, and extending its performance to high voltage applications, using cascaded (approach 1) or modified (approach 2) structures. In the first approach, analysis showed that with using only two DC sources in each cascaded module (..=2), the CAPUC1 and CAPUC2 generate the maximum number of voltage levels with a fixed number of DC sources and switches. Using more than two DC sources in each module, the CAPUC1 generates more voltage levels. Consequently, the CAPUC1 has the optimal structure among all discussed cascade structures. In the second one, the proposed modified structure can improve conventional PUC performance based on power switch ratings for high power applications. Design of a 147-level cascade inverter (based on the CAPUC1) and a novel 49-level modified structure are analyzed under optimal number of DC sources and power switches. Finally, experimental validations were performed by implementing laboratory prototypes. Experimental results in steady state and dynamics conditions showed that the proposed structures can generate output voltage with the lowest THD and highest controllability.

REFERENCES:

[1] H. Akagi, "Classification, Terminology, and Application of the Modular Multilevel Cascade Converter (MMCC)," in IEEE Transactions on Power Electronics, vol. 26, no. 11, pp. 3119-3130, Nov. 2011.

[2] S. Kouro et al., "Recent Advances and Industrial Applications of Multilevel Converters," in IEEE Transactions on Industrial Electronics, vol. 57, no. 8, pp. 2553-2580, Aug. 2010.

[3] J. Rodriguez, S. Bernet, B. Wu, J. O. Pontt and S. Kouro, "Multilevel Voltage-Source-Converter Topologies for Industrial Medium-Voltage Drives," in IEEE Transactions on Industrial Electronics, vol. 54, no. 6, pp. 2930-2945, Dec. 2007.

[4] H. Abu-Rub, J. Holtz, J. Rodriguez and G. Baoming, "Medium-Voltage Multilevel Converters—State of the Art, Challenges, and Requirements in Industrial Applications," in IEEE Transactions on Industrial Electronics, vol. 57, no. 8, pp. 2581-2596, Aug. 2010.

[5] X. Zha, L. Xiong, J. Gong and F. Liu, "Cascaded multilevel converter for medium-voltage motor drive capable of regenerating with part of cells," in IET Power Electronics, vol. 7, no. 5, pp. 1313-1320, May 2014.

Low Switching Frequency Based Asymmetrical Multilevel Inverter Topology With Reduced Switch Count

 ABSTRACT:

 The inceptions of multilevel inverters (MLI) have caught the attention of researchers for medium and high power applications. However, there has always been a need for a topology with a lower number of device count for higher efficiency and reliability. A new single-phase MLI topology has been proposed in this paper to reduce the number of switches in the circuit and obtain higher voltage level at the output. The basic unit of the proposed topology produces 13 levels at the output with three dc voltage sources and eight switches. Three extentions of the basic unit have been proposed in this paper. A detailed analysis of the proposed topology has been carried out to show the superiority of the proposed converter with respect to the other existing MLI topologies. Power loss analysis has been done using PLECS software, resulting in a maximum ef_ciency of 98.5%. Nearest level control (NLC) pulse-width modulation technique has been used to produce gate pulses for the switches to achieve better output voltage waveform. The various simulation results have been performed in the PLECS software and a laboratory setup has been used to show the feasibility of the proposed MLI topology.

KEYWORDS:

1.      DC - AC converter

2.      Multilevel inverter

3.      Reduce switch count

4.       Nearest level control (NLC)

SOFTWARE: MATLAB/SIMULINK

CONCLUSION:   

The paper presents a novel MLI topology with multiple exten- sion capabilities. The basic unit of the proposed topology produces 13 levels using eight unidirectional switches and three dc voltage sources. Three different extension of the basic unit has been proposed. The performance analysis of the basic unit of the proposed topology has been done and the comparative results with some recently proposed topologies in literature have been presented in the paper. Further, a power loss analysis of the dynamic losses (switching and conduction) in the MLI has also been presented, which gives the maximum efficicnecy of the basic unit as 98.5%. The power loss distribution in all the switches for different combination of loads have also been demonstrated in the paper. The performance of the proposed topology has been simulated with dynamic modulation indexes and different combination of loads using PLECS software. A prototype of the basic unit has been developed in the laboratory and the simulation results have been validated using the different expriemntal results considering different modulation indexes.

REFERENCES:

[1] S. Kouro, M. Malinowski, K. Gopakumar, J. Pou, L. G. Franquelo, B.Wu, J. Rodriguez, M. A. Perez, and J. I. Leon, ``Recent advances and industrial applications of multilevel converters,'' IEEE Trans. Ind. Electron., vol. 57, no. 8, pp. 2553_2580, Aug. 2010.

[2] H. Aburub, J. Holtz, and J. Rodriguez, ``Medium-voltage multilevel converters-state of the art, challenges, and requirements in industrial applications,'' IEEE Trans. Ind. Electron, vol. 57, no. 8, pp. 2581_2596, Dec. 2010.

[3] H. Akagi, ``Multilevel converters: Fundamental circuits and systems,'' Proc. IEEE, vol. 105, no. 11, pp. 2048_2065, Nov. 2017.

[4] J. I. Leon, S. Vazquez, and L. G. Franquelo, ``Multilevel converters: Control and modulation techniques for their operation and industrial appli- cations,'' Proc. IEEE, vol. 105, no. 11, pp. 2066_2081, Nov. 2017.

[5] J. Venkataramanaiah, Y. Suresh, and A. K. Panda, ``A review on symmet- ric, asymmetric, hybrid and single DC sources based multilevel inverter topologies,'' Renew. Sustain. Energy Rev., vol. 76, pp. 788_812, Sep. 2017.