ABSTRACT:
The
design of control circuit for a solar fed cascaded multilevel inverter to
reduce the number of semiconductor switches is presented in this study. The
design includes ‘binary’, ‘trinary’ and ‘modified multilevel
connection’ (MMC)-based
topologies suitable for varying input sources from solar photovoltaic’s (PV). In binary mode,
2Ns +1 − 1 output voltage levels are obtained where Ns is the number of
individual inverters. This is achieved by digital logic functions which
includes counters, flip-flops and logic gates. In trinary mode, 3Ns levels are
achieved by corresponding look-up table. MMC intends design in both control and
power circuits to provide corresponding output voltage levels by appropriate
switching sequences. Hence to obtain a 15-level inverter, the conventional
method requires 28 switches and in binary mode 12 switches are needed. In
trinary mode with the same 12 switches, 27 levels can be obtained whereas in
MMC only 7 switches are employed to achieve 15 levels. The advantage of these
three designs is in the reduction of total harmonic distortion by increasing
the levels. Simulations are carried out in MATLAB/Simulink and comparisons were
made. All the three topologies are experimentally investigated for a 3 kWp
solar PV plant and power quality indices were measured.
SOFTWARE: MATLAB/SIMULINK
Fig.1
Single stage 15-level inverter power circuit
Fig.
2 Solar PV with partial shaded condition for a 15-level CMLI
a Variation
of panel irradiance
b 15-level
output voltage waveform
Fig.
3 15-level output voltage waveform achieved from three stage inverter
a 15-level
output voltage waveform
b FFT
analysis for three stage 15-level CMLI
Fig.
4 Output voltage waveform and its corresponding harmonic spectrum
a 27-level
output voltage waveform
b FFT
analysis for three stage 27-level CMLI
Fig.
5 Output voltage waveform and its corresponding harmonic spectrum
a 15-level
output voltage waveform
b FFT
analysis for one stage 15-level CMLI
The
power quality improvement for a solar fed CMLI with reduced number of
semiconductor switches is investigated in this paper. The required 15-level
output is achieved with only 12 switches in binary mode and 7 switches in MMC mode.
In addition, 27-level output is obtained with 12 switches through trinary mode.
The mathematical model for solar PV is carried out which is considered as the
input to the inverter stages. A detailed simulation study is carried out for
various levels and comparison has been made. A 3 kWp solar PV fed CMLI is
implemented for all the three topologies and harmonics analysis was made. Based
on the observations, the proposed method provides the multiple advantages which
include reduced THD, less cost, simple design, minimum computational complexity
and the absence of transformers, boost converters, detailed look-up table and
filter circuit. Moreover, these methods are much suitable for standalone/grid
interacted PV systems to improve power quality.
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