Nine-level Asymmetrical Single Phase Multilevel Inverter Topology with Low switching frequency and Reduce device counts

ABSTRACT:

This paper presents a new asymmetrical single phase multilevel inverter topology capable of producing nine level output voltage with reduce device counts. In order to obtain the desired output voltage, dc sources are connected in all the combination of addition and subtraction through different switches. Proposed topology results in reduction of dc source, switch counts, losses, cost and size of the inverter. Comparison between the existing topologies shows that the proposed topology yields less component counts. Proposed topology is modeled and simulated using Matlab-Simulink software in order to verify the performance and feasibility of the circuit. A low frequency switching strategy is also proposed in this work. The results show that the proposed topology is capable to produce a nine-level output voltage with less number of component counts and acceptable harmonic distortion content.

KEYWORDS:

1.      Multilevel inverter

2.      Asymmetrical

3.      Total Harmonic Distortion (THD)

4.      Low-frequency switching

SOFTWARE: MATLAB/SIMULINK

 CIRCUIT DIAGRAM:

Fig. 1. Proposed nine level inverter topology.

EXPECTED SIMULATION RESULTS:

(a)     Output voltage waveform

(b)     Voltage Output Harmonic spectrum

(c)     Load current waveform

(d)     Load Current Harmonic spectrum

Fig. 2. Simulation Output results at 50Hz fundamental frequency for R = 150ohm, L= 240, P.F = 0.9

(a)     Output voltage waveform

(b)        Voltage Output Harmonic spectrum

(c)     Load current waveform

(d)     Load Current Harmonic spectrum

Fig. 3. Simulation Output results at 50Hz fundamental frequency for R = 150ohm, L= 240, P.F = 0.9

CONCLUSION:

In this paper a new single-phase multilevel inverter topology is presented. Proposed topology is capable of producing nine-level output voltage with reduce device counts. It can be used in medium and high power application with unequal dc sources. Different modes of operation are discussed in detail. On the bases of device counts, the proposed topology is compared with conventional as well as other asymmetrical nine-level inverter topologies presented in literature. Comparative study shows that, for nine level output, the proposed topology requires lesser component counts then the conventional and other topologies. Proposed circuit is modeled in Matlab/Simulink environment. Results obtained shows that topology works properly. Detailed Simulation analysis is carried out. THD obtained in the output voltage is 8.95% whereas the each harmonic order is < 5%, satisfies harmonic Standard (IEEE-519).

 REFERENCES:

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