ABSTRACT:
This paper presents a multilevel inverter that has been
conceptualized to reduce component count, particularly for a large number of
output levels. It comprises floating input dc sources alternately connected in
opposite polarities with one another through power switches. Each input dc
level appears in the stepped load voltage either individually or in additive
combinations with other input levels. This approach results in reduced number
of power switches as compared to classical topologies. The working principle of
the proposed topology is demonstrated with the help of a single-phase
five-level inverter. The topology is investigated through simulations and
validated experimentally on a laboratory prototype. An exhaustive comparison of
the proposed topology is made against the classical cascaded H-bridge topology.
KEYWORDS:
1.
Classical
topologies
2.
Multilevel
inverter (MLI)
3.
Pulse width
modulation (PWM)
4.
Reduced component
count
5.
Total harmonic distortion (THD)
SOFTWARE: MATLAB/SIMULINK
Fig.
1. Single-phase inverter based on the proposed topology with two input
sources.
EXPECTED SIMULATION RESULTS:
Fig.
2. (a) Reference and carrier waveforms for the proposed scheme for a
five-level
output. (b) Aggregated signal “a(t).”
Fig.
3. Switching pulse pattern for the five-level inverter.
Fig.
4. Simulation results. (a) Five-level voltage output. (b) Harmonic spectrum
of
the load voltage.
Fig.
5. Simulation results. (a) Load current waveform with an RL load (R =
2
Ω and L = 2 mH). (b) Harmonic spectrum of the load current.
As
MLIs are gaining interest, efforts are being directed toward reducing the
device count for increased number of output levels. A novel topology for MLIs
has been proposed in this paper to reduce the device count. The working
principle of the proposed topology has been explained, and mathematical formulations
corresponding to output voltage, source currents, voltage stresses on switches,
and power losses have been developed. Simulation studies performed on a
five-level inverter based on the proposed structure have been validated experimentally.
Comparison of the proposed topology with conventional topologies reveals that
the proposed topology significantly reduces the number of power switches and
associated gate driver circuits. Analytical comparisons on the basis of losses
and switch cost indicate that the proposed topology is highly competitive. The
proposed topology can be effectively employed for applications where isolated
dc sources are available. The advantage of the reduction in the device count, however,
imposes two limitations: 1) requirement of isolated dc sources as is the case
with the CHB topology and 2) curtailed modularity and fault-tolerant
capabilities as compared to the CHB topology.
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