This
paper deals with improving the voltage quality of sensitive loads from voltage
sags using dynamic voltage restorer (DVR). The higher active power requirement
associated with voltage phase jump compensation has caused a substantial rise
in size and cost of dc link energy storage system of DVR. The existing control
strategies either mitigate the phase jump or improve the utilization of dc link
energy by (i) reducing the amplitude of injected voltage, or (ii) optimizing
the dc bus energy support. In this paper, an enhanced sag compensation strategy
is proposed that mitigates the phase jump in the load voltage while improving
the overall sag compensation time. An analytical study shows that the proposed
method significantly increases the DVR sag support time (more than 50%)
compared with the existing phase jump compensation methods. This enhancement
can also be seen as a considerable reduction in dc link capacitor size for new
installation. The performance of proposed method is evaluated using simulation
study and finally, verified experimentally on a scaled lab prototype.
KEYWORDS:
1. Dynamic voltage restorer (DVR)
2. Voltage source inverter (VSI)
3. Voltage sag compensation
4. Voltage phase jump compensation
SOFTWARE: MATLAB/SIMULINK
CIRCUIT DIAGRAM:
Fig.
1 Basic DVR based system configuration.
Fig.
2. Simulation results for the proposed sag compensation method for 50% sag
depth. (a) PCC voltage, (b) load voltage, (c) DVR voltage, (d) DVR active and
reactive power, and (e) dc link voltage.
Fig.
3. Simulation results for the proposed sag compensation method for 23% sag
depth. (a) PCC voltage, (b) load voltage, (c) DVR voltage, (d) DVR active and
reactive power, and (e) dc link voltage.
CONCLUSION:
In
this paper an enhanced sag compensation scheme is proposed for capacitor
supported DVR. The proposed strategy improves the voltage quality of sensitive
loads by protecting them against the grid voltage sags involving the phase
jump. It also increases compensation time by operating in minimum active power
mode through a controlled transition once the phase jump is compensated. To
illustrate the effectiveness of the proposed method an analytical comparison is
carried out with the existing phase jump compensation schemes. It is shown that
compensation time can be extended from 10 to 25 cycles (considering presag
injection as the reference method) for the designed limit of 50% sag depth with
450 phase jump. Further extension in compensation time can be achieved for
intermediate sag depths. This extended compensation time can be seen as
considerable reduction in dc link capacitor size (for the studied case more
than 50%) for the new installation. The effectiveness of the proposed method is
evaluated through extensive simulations in MATLAB/Simulink and validated on a
scaled lab prototype experimentally. The experimental results demonstrate the
feasibility of the proposed phase jump compensation method for practical
applications.
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